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81338a4890
Summary: In PNaCl, most atomic instructions have their own @llvm.nacl.atomic.* function, each one, with a few exceptions, represents a consistent behaviour across all NaCl-supported targets. Unfortunately, the atomic RMW operations nand, [u]min, and [u]max aren't directly represented by any such @llvm.nacl.atomic.* function. This patch refines shouldExpandAtomicRMWInIR in TargetLowering so that a future `Le32TargetLowering` class can selectively inform the caller how the target desires the atomic RMW instruction to be expanded (ie via load-linked/store-conditional for ARM/AArch64, via cmpxchg for X86/others?, or not at all for Mips) if at all. This does not represent a behavioural change and as such no tests were added. Patch by: Richard Diamond. Reviewers: jfb Reviewed By: jfb Subscribers: jfb, aemerson, t.p.northover, llvm-commits Differential Revision: http://reviews.llvm.org/D7713 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231250 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
AsmParser | ||
Disassembler | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
Utils | ||
AArch64.h | ||
AArch64.td | ||
AArch64A53Fix835769.cpp | ||
AArch64A57FPLoadBalancing.cpp | ||
AArch64AddressTypePromotion.cpp | ||
AArch64AdvSIMDScalarPass.cpp | ||
AArch64AsmPrinter.cpp | ||
AArch64BranchRelaxation.cpp | ||
AArch64CallingConvention.h | ||
AArch64CallingConvention.td | ||
AArch64CleanupLocalDynamicTLSPass.cpp | ||
AArch64CollectLOH.cpp | ||
AArch64ConditionalCompares.cpp | ||
AArch64ConditionOptimizer.cpp | ||
AArch64DeadRegisterDefinitionsPass.cpp | ||
AArch64ExpandPseudoInsts.cpp | ||
AArch64FastISel.cpp | ||
AArch64FrameLowering.cpp | ||
AArch64FrameLowering.h | ||
AArch64InstrAtomics.td | ||
AArch64InstrFormats.td | ||
AArch64InstrInfo.cpp | ||
AArch64InstrInfo.h | ||
AArch64InstrInfo.td | ||
AArch64ISelDAGToDAG.cpp | ||
AArch64ISelLowering.cpp | ||
AArch64ISelLowering.h | ||
AArch64LoadStoreOptimizer.cpp | ||
AArch64MachineCombinerPattern.h | ||
AArch64MachineFunctionInfo.h | ||
AArch64MCInstLower.cpp | ||
AArch64MCInstLower.h | ||
AArch64PBQPRegAlloc.cpp | ||
AArch64PBQPRegAlloc.h | ||
AArch64PerfectShuffle.h | ||
AArch64PromoteConstant.cpp | ||
AArch64RegisterInfo.cpp | ||
AArch64RegisterInfo.h | ||
AArch64RegisterInfo.td | ||
AArch64SchedA53.td | ||
AArch64SchedA57.td | ||
AArch64SchedA57WriteRes.td | ||
AArch64SchedCyclone.td | ||
AArch64Schedule.td | ||
AArch64SelectionDAGInfo.cpp | ||
AArch64SelectionDAGInfo.h | ||
AArch64StorePairSuppress.cpp | ||
AArch64Subtarget.cpp | ||
AArch64Subtarget.h | ||
AArch64TargetMachine.cpp | ||
AArch64TargetMachine.h | ||
AArch64TargetObjectFile.cpp | ||
AArch64TargetObjectFile.h | ||
AArch64TargetTransformInfo.cpp | ||
AArch64TargetTransformInfo.h | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile |