Chad Rosier 67c325e9f0 [AArch64] Lower sdiv x, pow2 using add + select + shift. ... The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213758 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-23 14:57:52 +00:00
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AArch64	[AArch64] Lower sdiv x, pow2 using add + select + shift.	2014-07-23 14:57:52 +00:00
ARM	ARM: spot SBFX-compatbile code expressed with sign_extend_inreg	2014-07-23 13:59:12 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Fix two patterns that select i32's (for MIPS32r6) / i64's (for MIPS64r6)	2014-07-22 13:36:02 +00:00
MSP430
NVPTX	Add some tests for NVPTX lowering of cmpxchg	2014-07-21 22:54:44 +00:00
PowerPC	[SDAG] Make the DAGCombine worklist not grow endlessly due to duplicate	2014-07-23 07:08:53 +00:00
R600	[SDAG] Make the DAGCombine worklist not grow endlessly due to duplicate	2014-07-23 07:08:53 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: spot SBFX-compatbile code expressed with sign_extend_inreg	2014-07-23 13:59:12 +00:00
X86	[SKX] Enabling mask instructions: encoding, lowering	2014-07-23 14:49:42 +00:00
XCore