James Molloy 6c822eea47 Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163298 91177308-0d34-0410-b5e6-96231b3b80d8

2012-09-06 09:16:01 +00:00

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ARM

Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer.

2012-09-06 09:16:01 +00:00

CellSPU

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CPP

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Generic

BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle

2012-08-24 18:14:27 +00:00

Hexagon

LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the

2012-09-05 16:01:40 +00:00

MBlaze

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Mips

Fix UseInitArray option for MIPS target.

2012-09-05 06:17:17 +00:00

MSP430

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NVPTX

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PowerPC

Move tie checks into MachineVerifier::visitMachineOperand.

2012-09-04 18:38:28 +00:00

SPARC

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Thumb

Fix Thumb2 fixup kind in the integrated-as.

2012-09-01 15:06:36 +00:00

Thumb2

Use predication instead of pseudo-opcodes when folding into MOVCC.

2012-09-05 23:58:02 +00:00

X86

Add patterns for converting stores of subvector_extracts of lower 128-bits of a 256-bit vector to VMOVAPSmr/VMOVUPSmr.

2012-09-06 05:15:01 +00:00

XCore

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