Daniel Sanders 6ff1ef9931 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) ...

This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-30 14:45:14 +00:00

..

2r_vector_scalar.ll

[mips][msa] Implemented fill.d intrinsic.

2013-09-27 13:20:41 +00:00

2r.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

2rf_exup.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

2rf_float_int.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

2rf_fq.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

2rf_int_float.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

2rf_tq.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

2rf.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r_4r_widen.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r_4r.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r_splat.ll

[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics)

2013-10-30 13:07:44 +00:00

3r-a.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r-b.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r-c.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r-d.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r-i.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r-m.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r-p.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3r-s.ll

[mips][msa] Fix definition of SLD instruction.

2013-10-21 11:47:56 +00:00

3r-v.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3rf_4rf_q.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3rf_4rf.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3rf_exdo.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3rf_float_int.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3rf_int_float.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3rf_q.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

3rf.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

arithmetic_float.ll

[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)

2013-10-23 10:36:52 +00:00

arithmetic.ll

[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)

2013-10-11 10:50:42 +00:00

basic_operations_float.ll

[mips][msa] Added support for build_vector for v4f32 and v2f64.

2013-10-15 13:14:41 +00:00

basic_operations.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

bit.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

bitcast.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

bitwise.ll

[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)

2013-10-30 14:45:14 +00:00

compare_float.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

compare.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

elm_copy.ll

[mips][msa] Implemented copy_[us].d intrinsic.

2013-09-27 13:04:21 +00:00

elm_cxcmsa.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

elm_insv.ll

[mips][msa] Implemented insert.d intrinsic.

2013-09-27 13:36:54 +00:00

elm_move.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

elm_shift_slide.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

i5_ld_st.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

i5-a.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

i5-b.ll

[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)

2013-10-30 14:45:14 +00:00

i5-c.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

i5-m.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

i5-s.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

i8.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

i10.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

llvm-stress-s525530439.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

llvm-stress-s997348632.ll

[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64

2013-09-27 12:17:32 +00:00

llvm-stress-s1935737938.ll

[mips][msa] Added support for MSA registers to copyPhysReg

2013-09-27 12:03:51 +00:00

llvm-stress-s3997499501.ll

[mips][msa] Added a regression test that depended on multiple patches to pass.

2013-10-18 09:52:21 +00:00

llvm-stress-sz1-s742806235.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

shuffle.ll

[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)

2013-09-27 11:48:57 +00:00

special.ll

[mips][msa] Added lsa instruction

2013-10-17 13:38:20 +00:00

spill.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

vec.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00

vecs10.ll

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

2013-09-27 10:08:31 +00:00