Robert Khasanov 7017934668 [SKX] Enabling load/store instructions: encoding ... Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS, Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214719 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-04 14:35:15 +00:00
..
AArch64	Revert "r214669 - MachineCombiner Pass for selecting faster instruction"	2014-08-04 05:10:33 +00:00
ARM	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
CPP
Generic
Hexagon
Inputs
Mips	llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll: Add explicit -mtriple=(mips|mipsel)-linux on 4 lines.	2014-08-01 22:15:38 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Swap arguments to vpkuhum/vpkuwum on little-endian	2014-08-04 13:53:40 +00:00
R600	R600/SI: Fix extra whitespace in asm str	2014-08-03 05:27:14 +00:00
SPARC
SystemZ
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
X86	[SKX] Enabling load/store instructions: encoding	2014-08-04 14:35:15 +00:00
XCore