llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-10 01:10:48 +00:00

History

Tom Stellard cd0f245864 R600/SI: Add support for 64-bit loads https://bugs.freedesktop.org/show_bug.cgi?id=65873 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186339 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-15 19:00:09 +00:00
..
64bit-kernel-args.ll	R600/SI: Add support for f64 kernel arguments	2013-07-12 18:15:26 +00:00
128bit-kernel-args.ll	R600/SI: Add support for v4i32 and v4f32 kernel args	2013-06-25 02:39:25 +00:00
add.ll	R600/SI: Expand add for v2i32 and v4i32	2013-06-20 21:55:30 +00:00
and.ll	R600/SI: Expand and of v2i32/v4i32 for SI	2013-06-25 13:55:23 +00:00
bfe_uint.ll
bfi_int.ll
call_fs.ll
cf_end.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
elf.ll
elf.r600.ll
fabs.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
fadd64.ll	R600/SI: Add initial double precision support for SI	2013-07-12 18:14:56 +00:00
fadd.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
fcmp64.ll	R600/SI: Implement select and compares for SI	2013-07-12 18:15:19 +00:00
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll
fconst64.ll	R600: Reapply testcase from r186178, the big endian issue should be fixed by r186196.	2013-07-12 21:54:43 +00:00
fdiv64.ll	R600/SI: Add initial double precision support for SI	2013-07-12 18:14:56 +00:00
fdiv.ll	R600: Support schedule and packetization of trans-only inst	2013-06-29 19:32:43 +00:00
fetch-limits.r600.ll	R600: Fix the fetch limits for R600 generation GPUs	2013-06-07 20:28:55 +00:00
fetch-limits.r700+.ll	R600: Fix the fetch limits for R600 generation GPUs	2013-06-07 20:28:55 +00:00
floor.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
fmad.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
fmax.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
fmin.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
fmul64.ll	R600/SI: Add initial double precision support for SI	2013-07-12 18:14:56 +00:00
fmul.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
fmul.v4f32.ll
fp_to_sint.ll	R600: Support schedule and packetization of trans-only inst	2013-06-29 19:32:43 +00:00
fp_to_uint.ll	R600: Support schedule and packetization of trans-only inst	2013-06-29 19:32:43 +00:00
fsqrt.ll	R600/SI: Add fsqrt pattern for SI	2013-07-12 18:15:13 +00:00
fsub64.ll	R600/SI: Add double precision fsub pattern for SI	2013-07-12 18:15:08 +00:00
fsub.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll
imm.ll
indirect-addressing.ll	R600: Fix calculation of stack offset in AMDGPUFrameLowering	2013-06-07 20:52:05 +00:00
jump-address.ll	R600: Do not predicated basic block with multiple alu clause	2013-07-09 15:03:33 +00:00
kcache-fold.ll
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll
llvm.AMDGPU.barrier.local.ll	R600: Add support for GROUP_BARRIER instruction	2013-06-28 15:46:59 +00:00
llvm.AMDGPU.cube.ll	R600: Use new getNamedOperandIdx function generated by TableGen	2013-06-25 21:22:18 +00:00
llvm.AMDGPU.imax.ll
llvm.AMDGPU.imin.ll
llvm.AMDGPU.mul.ll	R600: Schedule copy from phys register at beginning of block	2013-06-05 20:27:35 +00:00
llvm.AMDGPU.tex.ll
llvm.AMDGPU.trunc.ll
llvm.AMDGPU.umax.ll
llvm.AMDGPU.umin.ll
llvm.cos.ll	R600: Use DAG lowering pass to handle fcos/fsin	2013-07-09 15:03:11 +00:00
llvm.pow.ll	R600: Support schedule and packetization of trans-only inst	2013-06-29 19:32:43 +00:00
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll
llvm.SI.resinfo.ll
llvm.SI.sample.ll
llvm.SI.sampled.ll	R600/SI: Add intrinsics for texture sampling with user derivatives	2013-07-10 16:36:36 +00:00
llvm.SI.tid.ll	R600/SI: Add intrinsic for retrieving the current thread ID	2013-07-10 16:36:52 +00:00
llvm.sin.ll	R600: Use DAG lowering pass to handle fcos/fsin	2013-07-09 15:03:11 +00:00
load64.ll	R600/SI: Add initial double precision support for SI	2013-07-12 18:14:56 +00:00
load-input-fold.ll
load.ll	R600/SI: Add support for 64-bit loads	2013-07-15 19:00:09 +00:00
load.vec.ll	R600: Expand v2i32 load/store instead of custom lowering	2013-06-20 21:55:23 +00:00
local-memory-two-objects.ll	R600/SI: Initial local memory support	2013-07-10 16:37:07 +00:00
local-memory.ll	R600/SI: Initial local memory support	2013-07-10 16:37:07 +00:00
loop-address.ll
lshl.ll
lshr.ll
mul.ll	R600/SI: Expand mul of v2i32/v4i32 for SI	2013-06-25 13:55:26 +00:00
mulhu.ll
or.ll	R600/SI: Expand or of v2i32/v4i32 for SI	2013-06-25 13:55:29 +00:00
packetizer.ll	R600: Fix typo in R600Schedule.td	2013-06-25 02:39:20 +00:00
predicates.ll
pv-packing.ll	R600: PV stores Reg id, not index	2013-06-17 20:16:40 +00:00
pv.ll
r600-encoding.ll
README
reciprocal.ll
rotr.ll
rv7x0_count3.ll	R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.	2013-06-17 20:16:26 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
set-dx10.ll
setcc.ll	R600: Add v2i32 test for setcc on evergreen	2013-06-25 13:55:49 +00:00
seto.ll
setuo.ll
shl.ll	R600/SI: Expand shl of v2i32/v4i32 for SI	2013-06-25 13:55:32 +00:00
short-args.ll
sign_extend.ll
sint_to_fp.ll
sra.ll	R600/SI: Add support for 64-bit loads	2013-07-15 19:00:09 +00:00
srl.ll	R600/SI: Expand srl of v2i32/v4i32 for SI	2013-06-25 13:55:37 +00:00
store.ll	R600/SI: Report unaligned memory accesses as legal for > 32-bit types	2013-06-25 02:39:35 +00:00
store.r600.ll
sub.ll	R600/SI: Expand sub for v2i32 and v4i32 for SI	2013-06-20 21:55:37 +00:00
swizzle-export.ll	R600: Fix a rare bug where swizzle optimization returns wrong values	2013-07-09 15:03:25 +00:00
tex-clause-antidep.ll	R600: Anti dep better handled in tex clause	2013-06-07 23:30:26 +00:00
texture-input-merge.ll	R600: Add a pass that merge Vector Register	2013-06-05 21:38:04 +00:00
udiv.ll	R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG	2013-06-25 13:55:43 +00:00
uint_to_fp.ll
uitofp.ll
unsupported-cc.ll
urecip.ll
urem.ll	R600/SI: Expand urem of v2i32/v4i32 for SI	2013-06-25 13:55:46 +00:00
vertex-fetch-encoding.ll	Prefix failing commands with not to make clear they are expected to fail.	2013-07-03 16:41:29 +00:00
vselect.ll	R600: Add v2i32 test for vselect	2013-06-25 13:55:54 +00:00
vtx-schedule.ll
work-item-intrinsics.ll
xor.ll	R600/SI: Expand xor v2i32/v4i32	2013-06-25 13:55:52 +00:00

README

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.