llvm-6502/lib/Target/Sparc
Chris Lattner 749c6f6b5e rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 07:27:27 +00:00
..
DelaySlotFiller.cpp rename TargetInstrDescriptor -> TargetInstrDesc. 2008-01-07 07:27:27 +00:00
FPMover.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
Makefile remove attribution from lib Makefiles. 2007-12-29 20:09:26 +00:00
README.txt
Sparc.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
Sparc.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcAsmPrinter.cpp Add new shorter predicates for testing machine operands for various types: 2007-12-30 23:10:15 +00:00
SparcInstrFormats.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcInstrInfo.cpp Move even more functionality from MRegisterInfo into TargetInstrInfo. 2008-01-07 01:35:02 +00:00
SparcInstrInfo.h Move even more functionality from MRegisterInfo into TargetInstrInfo. 2008-01-07 01:35:02 +00:00
SparcInstrInfo.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcISelDAGToDAG.cpp Rename SSARegMap -> MachineRegisterInfo in keeping with the idea 2007-12-31 04:13:23 +00:00
SparcRegisterInfo.cpp Move even more functionality from MRegisterInfo into TargetInstrInfo. 2008-01-07 01:35:02 +00:00
SparcRegisterInfo.h Move even more functionality from MRegisterInfo into TargetInstrInfo. 2008-01-07 01:35:02 +00:00
SparcRegisterInfo.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcSubtarget.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcSubtarget.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcTargetAsmInfo.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcTargetAsmInfo.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcTargetMachine.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcTargetMachine.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots