Michel Danzer 74bf7a8467 R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32 ...

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175733 91177308-0d34-0410-b5e6-96231b3b80d8

2013-02-21 08:57:10 +00:00

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AArch64

AArch64: remove ConstantIsland pass & put literals in separate section.

2013-02-15 09:33:43 +00:00

ARM

DAGCombiner: Fold pointless truncate, bitcast, buildvector series

2013-02-20 21:33:32 +00:00

CPP

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Generic

For inline asm:

2013-01-11 18:12:39 +00:00

Hexagon

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

MBlaze

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Mips

Expand the sel pseudo/macro. This generates basic blocks where previously

2013-02-21 04:22:38 +00:00

MSP430

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NVPTX

[NVPTX] Disable vector registers

2013-02-12 14:18:49 +00:00

PowerPC

PPCDAGToDAGISel::PostprocessISelDAG()

2013-02-21 00:38:25 +00:00

R600

R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32

2013-02-21 08:57:10 +00:00

SI

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SPARC

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Thumb

Fix thumbv5e frame lowering assertion failure.

2013-02-20 12:21:33 +00:00

Thumb2

ARM: Allocation hints must make sure to be in the alloc order.

2013-02-19 18:55:36 +00:00

X86

Fix PR15267

2013-02-20 18:04:21 +00:00

XCore

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