Cameron Zwarich d78ebe1e12 Remove a check from ARM shifted operand isel helper methods, which were blocking ... merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-05 23:38:50 +00:00
..
Alpha	Convert more tests over to the new atomic instructions.	2011-09-26 21:30:17 +00:00
ARM	Remove a check from ARM shifted operand isel helper methods, which were blocking	2011-10-05 23:38:50 +00:00
Blackfin	more tests not making the jump into the brave new world.	2011-07-09 16:57:10 +00:00
CBackend	Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported	2011-09-26 06:44:27 +00:00
CellSPU	Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.	2011-09-02 10:05:01 +00:00
CPP
Generic	PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval	2011-09-26 06:13:20 +00:00
MBlaze
Mips	Move CHECK after entry label.	2011-10-03 21:24:30 +00:00
MSP430
PowerPC	Convert more tests over to the new atomic instructions.	2011-09-26 21:30:17 +00:00
PTX	PTX: Add new patterns for bitconvert and any_extend	2011-09-29 01:13:12 +00:00
SPARC
SystemZ
Thumb	Convert more tests to new atomic instructions.	2011-09-26 21:36:10 +00:00
Thumb2	ARM Darwin default relocation model is PIC.	2011-09-30 17:41:35 +00:00
X86	Filecheck-ize.	2011-09-30 23:40:29 +00:00
XCore	Associate a MemOperand with LDWCP nodes introduced during ISel.	2011-09-12 14:43:23 +00:00