llvm-6502/lib/Target/Sparc
Stuart Hastings a901129169 Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods.  Radar 9002173.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16 16:23:55 +00:00
..
TargetInfo add support for the sparcv9-*-* target triple to turn on 2010-02-04 06:34:01 +00:00
CMakeLists.txt Update CMake stuff 2011-01-10 12:39:23 +00:00
DelaySlotFiller.cpp Prevent IMPLICIT_DEF/KILL to become a delay filler instruction in SPARC backend. 2011-02-12 19:02:33 +00:00
FPMover.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
Makefile move all the target's asmprinters into the main target. The piece 2010-11-14 18:43:56 +00:00
README.txt Add JIT support to the TODO list (test commit) 2010-03-01 10:40:41 +00:00
Sparc.h add support for the sparcv9-*-* target triple to turn on 2010-02-04 06:34:01 +00:00
Sparc.td fix emacs language spec's, patch by Edmund Grimley-Evans! 2010-08-17 16:20:04 +00:00
SparcAsmPrinter.cpp Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to 2011-01-12 03:52:59 +00:00
SparcCallingConv.td Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 2011-01-22 13:05:16 +00:00
SparcFrameLowering.cpp Teach frame lowering to ignore debug values after the terminators. 2011-01-13 21:28:52 +00:00
SparcFrameLowering.h Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp Implement AnalyzeBranch in Sparc Backend. 2011-01-16 03:15:11 +00:00
SparcInstrInfo.h Implement AnalyzeBranch in Sparc Backend. 2011-01-16 03:15:11 +00:00
SparcInstrInfo.td Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 2011-01-22 11:36:24 +00:00
SparcISelDAGToDAG.cpp rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for 2010-12-21 02:38:05 +00:00
SparcISelLowering.cpp Swap VT and DebugLoc operands of getExtLoad() for consistency with 2011-02-16 16:23:55 +00:00
SparcISelLowering.h Sparc backend: 2011-01-21 22:00:00 +00:00
SparcMachineFunctionInfo.h Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 2011-01-22 13:05:16 +00:00
SparcMCAsmInfo.cpp Don't pass StringRef by reference. 2010-07-14 22:38:02 +00:00
SparcMCAsmInfo.h Don't pass StringRef by reference. 2010-07-14 22:38:02 +00:00
SparcRegisterInfo.cpp Move hasFP() and few related hooks to TargetFrameInfo. 2010-11-18 21:19:35 +00:00
SparcRegisterInfo.h Move hasFP() and few related hooks to TargetFrameInfo. 2010-11-18 21:19:35 +00:00
SparcRegisterInfo.td Multiple SPARC backend fixes: added Y register; updated select_cc, subx, subxcc defs/uses; 2010-12-28 20:39:17 +00:00
SparcSelectionDAGInfo.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SparcSelectionDAGInfo.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SparcSubtarget.cpp add support for the sparcv9-*-* target triple to turn on 2010-02-04 06:34:01 +00:00
SparcSubtarget.h add support for the sparcv9-*-* target triple to turn on 2010-02-04 06:34:01 +00:00
SparcTargetMachine.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
SparcTargetMachine.h Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support