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llvm-6502/test/CodeGen/Mips
History
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cconv
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Fast-ISel
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llvm-ir
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mips32r6
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mips64r6
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msa
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2008-06-05-Carry.ll
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2008-07-03-SRet.ll
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2008-07-06-fadd64.ll
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2008-07-07-Float2Int.ll
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2008-07-07-FPExtend.ll
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2008-07-07-IntDoubleConvertions.ll
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2008-07-15-InternalConstant.ll
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2008-07-15-SmallSection.ll
Remove +.
2011-09-21 17:43:48 +00:00
2008-07-16-SignExtInReg.ll
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2008-07-22-Cstpool.ll
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2008-07-23-fpcmp.ll
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2008-07-29-icmp.ll
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2008-07-31-fcopysign.ll
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2008-08-01-AsmInline.ll
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2008-08-03-fabs64.ll
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2008-08-03-ReturnDouble.ll
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2008-08-04-Bitconvert.ll
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2008-08-06-Alloca.ll
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2008-08-07-CC.ll
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2008-08-07-FPRound.ll
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2008-08-08-bswap.ll
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2008-08-08-ctlz.ll
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2008-10-13-LegalizerBug.ll
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2008-11-10-xint_to_fp.ll
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2009-11-16-CstPoolLoad.ll
[mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.
2014-02-20 14:58:19 +00:00
2010-07-20-Switch.ll
[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point
2014-04-14 16:00:28 +00:00
2010-11-09-CountLeading.ll
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2010-11-09-Mul.ll
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2011-05-26-BranchKillsVreg.ll
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2012-12-12-ExpandMemcpy.ll
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2013-11-18-fp64-const0.ll
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abicalls.ll
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abiflags32.ll
[mips] Do not emit '.module fp=...' unless we really need to.
2014-07-21 15:25:24 +00:00
abiflags-xx.ll
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addc.ll
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addi.ll
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addressing-mode.ll
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align16.ll
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alloca16.ll
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alloca.ll
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analyzebranch.ll
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and1.ll
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asm-large-immediate.ll
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atomic.ll
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atomicops.ll
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beqzc1.ll
Make all the conditional Mips 16 branches get initially set for the
2013-11-15 02:21:52 +00:00
beqzc.ll
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biggot.ll
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blez_bgez.ll
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blockaddr.ll
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br-jmp.ll
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brconeq.ll
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brconeqk.ll
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brconeqz.ll
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brconge.ll
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brcongt.ll
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brconle.ll
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brconlt.ll
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brconne.ll
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brconnek.ll
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brconnez.ll
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brdelayslot.ll
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brind.ll
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brsize3.ll
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brsize3a.ll
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bswap.ll
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buildpairextractelementf64.ll
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cache-intrinsic.ll
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call-optimization.ll
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cfi_offset.ll
[mips] Emit two CFI offset directives per double precision SDC1/LDC1
2014-07-10 22:23:30 +00:00
check-noat.ll
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ci2.ll
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cmov.ll
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cmplarge.ll
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const1.ll
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const4a.ll
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const6.ll
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const6a.ll
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const-mult.ll
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constantfp0.ll
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countleading.ll
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cprestore.ll
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ctlz-v.ll
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ctlz.ll
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cttz-v.ll
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DbgValueOtherTargets.test
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disable-tail-merge.ll
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div_rem.ll
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div.ll
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divrem.ll
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divu_remu.ll
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divu.ll
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double2int.ll
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dsp-patterns-cmp-vselect.ll
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dsp-patterns.ll
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dsp-r1.ll
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dsp-r2.ll
MIPS DSP: add operands to make sure instruction strings are being matched.
2012-09-28 21:23:16 +00:00
dsp-vec-load-store.ll
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eh-dwarf-cfa.ll
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eh-return32.ll
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eh-return64.ll
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eh.ll
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ehframe-indirect.ll
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elf_eflags.ll
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emit-big-cst.ll
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ex2.ll
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extins.ll
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f16abs.ll
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fabs.ll
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fastcc.ll
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fcmp.ll
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fcopysign-f32-f64.ll
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fcopysign.ll
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fixdfsf.ll
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fmadd1.ll
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fneg.ll
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fp16instrinsmc.ll
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fp16mix.ll
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fp16static.ll
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fp64a.ll
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fp-indexed-ls.ll
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fp-spill-reload.ll
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fpbr.ll
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fpneeded.ll
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fpnotneeded.ll
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fptr2.ll
[Mips] Adjust float ABI settings in case of MIPS16 mode.
2013-11-19 12:20:17 +00:00
fpxx.ll
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frame-address.ll
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frem.ll
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global-address.ll
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global-pointer-reg.ll
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gpreg-lazy-binding.ll
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gprestore.ll
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helloworld.ll
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hf1_body.ll
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hf16_1.ll
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hf16call32_body.ll
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hf16call32.ll
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hfptrcall.ll
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i32k.ll
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i64arg.ll
[mips] Make sure there is a chain edge dependency between loads that read
2013-11-09 02:38:51 +00:00
imm.ll
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indirectcall.ll
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init-array.ll
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inlineasm64.ll
Have getRegForInlineAsmConstraint return the correct register class when target
2012-01-04 02:45:01 +00:00
inlineasm_constraint.ll
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inlineasm-cnstrnt-bad-I-1.ll
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inlineasm-cnstrnt-bad-J.ll
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inlineasm-cnstrnt-bad-K.ll
Add support for the inline asm constraint 'K'.
2012-05-07 05:46:29 +00:00
inlineasm-cnstrnt-bad-L.ll
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inlineasm-cnstrnt-bad-N.ll
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inlineasm-cnstrnt-bad-O.ll
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inlineasm-cnstrnt-bad-P.ll
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inlineasm-cnstrnt-reg64.ll
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inlineasm-cnstrnt-reg.ll
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inlineasm-operand-code.ll
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inlineasmmemop.ll
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int-to-float-conversion.ll
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internalfunc.ll
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jtstat.ll
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l3mc.ll
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largeimm1.ll
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largeimmprinting.ll
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lazy-binding.ll
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lb1.ll
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lbu1.ll
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lcb2.ll
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lcb3c.ll
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lcb4a.ll
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lcb5.ll
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lh1.ll
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lhu1.ll
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lit.local.cfg
Reduce verbiage of lit.local.cfg files
2014-06-09 22:42:55 +00:00
llcarry.ll
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load-store-left-right.ll
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longbranch.ll
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machineverifier.ll
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madd-msub.ll
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mature-mc-support.ll
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mbrsize4a.ll
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memcpy.ll
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micromips-atomic.ll
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micromips-directives.ll
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micromips-jal.ll
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micromips-load-effective-address.ll
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mips16_32_1.ll
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mips16_32_3.ll
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mips16_32_4.ll
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mips16_32_5.ll
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mips16_32_6.ll
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mips16_32_7.ll
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mips16_32_8.ll
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mips16_32_9.ll
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mips16_32_10.ll
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mips16_fpret.ll
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mips16-hf-attr.ll
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mips16ex.ll
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mips16fpe.ll
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mips64-f128-call.ll
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mips64-f128.ll
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mips64-libcall.ll
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mips64-sret.ll
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mips64directive.ll
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mips64ext.ll
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mips64extins.ll
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mips64fpimm0.ll
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mips64fpldst.ll
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mips64imm.ll
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mips64instrs.ll
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mips64intldst.ll
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mips64lea.ll
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mips64muldiv.ll
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mips64shift.ll
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mipslopat.ll
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misha.ll
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mno-ldc1-sdc1.ll
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mul.ll
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mulll.ll
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mulull.ll
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nacl-align.ll
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nacl-branch-delay.ll
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nacl-reserved-regs.ll
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neg1.ll
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no-odd-spreg.ll
[mips] Do not emit '.module [no]oddspreg' unless we really need to.
2014-07-21 10:45:47 +00:00
nomips16.ll
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not1.ll
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null-streamer.ll
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null.ll
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o32_cc_byval.ll
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o32_cc_vararg.ll
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o32_cc.ll
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octeon_popcnt.ll
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octeon.ll
[mips] Add more Octeon cnMips instructions
2014-04-02 18:40:43 +00:00
optimize-fp-math.ll
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optimize-pic-o0.ll
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or1.ll
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powif64_16.ll
[Mips] Adjust float ABI settings in case of MIPS16 mode.
2013-11-19 12:20:17 +00:00
prevent-hoisting.ll
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private.ll
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ra-allocatable.ll
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rdhwr-directives.ll
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rem.ll
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remat-immed-load.ll
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remu.ll
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return_address.ll
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return-vector.ll
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rotate.ll
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s2rem.ll
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sb1.ll
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sel1c.ll
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sel2c.ll
[mips] Small code generation improvement for conditional operator (select)
2013-12-05 12:07:05 +00:00
select.ll
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selectcc.ll
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seleq.ll
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seleqk.ll
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selgek.ll
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selgt.ll
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selle.ll
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selltk.ll
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selne.ll
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selnek.ll
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selpat.ll
Expand pseudos/macros for Selt. This is the last of the complex
2013-02-23 03:09:56 +00:00
selTBteqzCmpi.ll
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selTBtnezCmpi.ll
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selTBtnezSlti.ll
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setcc-se.ll
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seteq.ll
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seteqz.ll
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setge.ll
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setgek.ll
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setle.ll
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setlt.ll
Expand pseudos/macros:
2013-02-20 05:45:15 +00:00
setltk.ll
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setne.ll
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setuge.ll
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setugt.ll
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setule.ll
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setult.ll
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setultk.ll
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sh1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
shift-parts.ll
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simplebr.ll
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sint-fp-store_pattern.ll
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sitofp-selectcc-opt.ll
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sll1.ll
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sll2.ll
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small-section-reserve-gp.ll
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spill-copy-acreg.ll
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sr1.ll
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sra1.ll
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sra2.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
srl1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
srl2.ll
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stack-alignment.ll
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stackcoloring.ll
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stacksize.ll
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start-asm-file.ll
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stchar.ll
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stldst.ll
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sub1.ll
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sub2.ll
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swzero.ll
Don't modify MO while use_iterator is still pointing to it.
2012-08-09 22:08:24 +00:00
tail16.ll
Fix a problem with mips16 stubs when calls are transformed during
2013-12-18 23:57:48 +00:00
tailcall.ll
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tls16_2.ll
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tls16.ll
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tls-alias.ll
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tls-models.ll
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tls.ll
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tnaked.ll
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trap1.ll
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trap.ll
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uitofp.ll
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ul1.ll
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unalignedload.ll
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vector-load-store.ll
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vector-setcc.ll
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weak.ll
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xor1.ll
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zeroreg.ll
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