llvm-6502/lib/Target/AArch64
Quentin Colombet 7f4f923aa5 [AArch64] Fix registerAllocator assigns same register for base and wback in
pre/post-index load and store.

Patch by Steven Wu <stevenwu@apple.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215390 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 21:39:53 +00:00
..
AsmParser
Disassembler
InstPrinter
MCTargetDesc If available, pass down the Fixup object to EvaluateAsRelocatable. 2014-08-10 11:35:12 +00:00
TargetInfo AArch64: stop trying to take control of all UnknownArch triples. 2014-08-08 08:27:44 +00:00
Utils
AArch64.h [AArch64] Add an FP load balancing pass for Cortex-A57 2014-08-08 12:33:21 +00:00
AArch64.td
AArch64A57FPLoadBalancing.cpp AArch64: avoid deleting the current iterator in a loop. 2014-08-08 17:31:52 +00:00
AArch64AddressTypePromotion.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp
AArch64CallingConvention.td Remove the target machine from CCState. Previously it was only used 2014-08-06 18:45:26 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
AArch64DeadRegisterDefinitionsPass.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
AArch64ExpandPseudoInsts.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
AArch64FastISel.cpp [FastISel][AArch64] Attach MachineMemOperands to load and store instructions. 2014-08-08 17:24:10 +00:00
AArch64FrameLowering.cpp Fix typos: 2014-08-11 18:04:46 +00:00
AArch64FrameLowering.h
AArch64InstrAtomics.td
AArch64InstrFormats.td [AArch64] Fix registerAllocator assigns same register for base and wback in 2014-08-11 21:39:53 +00:00
AArch64InstrInfo.cpp Resolving some type truncation warnings in MSVC (enum to bool in this case). No functional changes intended. 2014-08-09 19:53:34 +00:00
AArch64InstrInfo.h MachineCombiner Pass for selecting faster instruction sequence on AArch64 2014-08-07 21:40:58 +00:00
AArch64InstrInfo.td
AArch64ISelDAGToDAG.cpp
AArch64ISelLowering.cpp Remove the target machine from CCState. Previously it was only used 2014-08-06 18:45:26 +00:00
AArch64ISelLowering.h
AArch64LoadStoreOptimizer.cpp
AArch64MachineCombinerPattern.h MachineCombiner Pass for selecting faster instruction sequence on AArch64 2014-08-07 21:40:58 +00:00
AArch64MachineFunctionInfo.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RegisterInfo.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
AArch64Subtarget.cpp
AArch64Subtarget.h [AArch64] Add a few isTarget* API to AArch64 Subtarget. 2014-08-06 16:56:58 +00:00
AArch64TargetMachine.cpp [AArch64] Add an FP load balancing pass for Cortex-A57 2014-08-08 12:33:21 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp Teach the SLP Vectorizer that keeping some values live over a callsite can have a cost. 2014-08-05 12:30:34 +00:00
CMakeLists.txt [AArch64] Add an FP load balancing pass for Cortex-A57 2014-08-08 12:33:21 +00:00
LLVMBuild.txt
Makefile