Bruno Cardoso Lopes 807360ab08 [x86] Combine x86mmx/i64 to v2i64 conversion to use scalar_to_vector ... Handle the poor codegen for i64/x86xmm->v2i64 (%mm -> %xmm) moves. Instead of using stack store/load pair to do the job, use scalar_to_vector directly, which in the MMX case can use movq2dq. This was the current behavior prior to improvements for vector legalization of extloads in r213897. This commit fixes the regression and as a side-effect also remove some unnecessary shuffles. In the new attached testcase, we go from: pshufw $-18, (%rdi), %mm0 movq %mm0, -8(%rsp) movq -8(%rsp), %xmm0 pshufd $-44, %xmm0, %xmm0 movd %xmm0, %eax ... To: pshufw $-18, (%rdi), %mm0 movq2dq %mm0, %xmm0 movd %xmm0, %eax ... Differential Revision: http://reviews.llvm.org/D7126 rdar://problem/19413324 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226953 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-23 22:44:16 +00:00
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AArch64	DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))	2015-01-21 23:17:19 +00:00
ARM	This patch fixes issue with lowering below mentioned pattern :-	2015-01-23 09:10:03 +00:00
CPP
Generic
Hexagon	[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.	2015-01-21 18:13:15 +00:00
Inputs
Mips	[mips] Add registers and ALL check prefix to octeon test case.	2015-01-20 16:14:02 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2	2015-01-19 07:20:27 +00:00
R600	R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()	2015-01-23 22:05:45 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[x86] Combine x86mmx/i64 to v2i64 conversion to use scalar_to_vector	2015-01-23 22:44:16 +00:00
XCore