Hal Finkel 827b7a070d Add support for the PowerPC-specific inline asm Z constraint and y modifier. ... The Z constraint specifies an r+r memory address, and the y modifier expands to the "r, r" in the asm string. For this initial implementation, the base register is forced to r0 (which has the special meaning of 0 for r+r addressing on PowerPC) and the full address is taken in the second register. In the future, this should be improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167388 91177308-0d34-0410-b5e6-96231b3b80d8		2012-11-05 18:18:42 +00:00
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ARM	Vext Lowering was missing opportunities	2012-11-02 21:32:17 +00:00
CellSPU	Fix broken tests.	2012-10-02 15:49:34 +00:00
CPP
Generic	BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle	2012-08-24 18:14:27 +00:00
Hexagon	LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the	2012-09-05 16:01:40 +00:00
MBlaze
Mips	[mips] Set flag neverHasSideEffects flag on floating point conversion	2012-11-03 00:53:12 +00:00
MSP430	Fix fallout from RegInfo => FrameLowering refactoring on MSP430.	2012-10-17 17:37:11 +00:00
NVPTX
PowerPC	Add support for the PowerPC-specific inline asm Z constraint and y modifier.	2012-11-05 18:18:42 +00:00
SPARC	Use TargetTransformInfo to control switch-to-lookup table transformation	2012-10-30 11:23:25 +00:00
Thumb	Fix Thumb2 fixup kind in the integrated-as.	2012-09-01 15:06:36 +00:00
Thumb2	Add GPRPair Register class to ARM.	2012-10-26 21:29:15 +00:00
X86	test/CodeGen/X86/fp-fast.ll: Add +avx.	2012-11-01 02:13:45 +00:00
XCore