llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-20 09:30:43 +00:00

History

Duncan Sands 83ec4b6711 Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8		2008-06-06 12:08:01 +00:00
..
Alpha.h	Change target-specific classes to use more precise static types.	2008-05-14 01:58:56 +00:00
Alpha.td
AlphaAsmPrinter.cpp	Add CommonLinkage; currently tentative definitions	2008-05-14 20:12:51 +00:00
AlphaBranchSelector.cpp
AlphaCodeEmitter.cpp
AlphaInstrFormats.td
AlphaInstrInfo.cpp
AlphaInstrInfo.h	Change target-specific classes to use more precise static types.	2008-05-14 01:58:56 +00:00
AlphaInstrInfo.td
AlphaISelDAGToDAG.cpp	Wrap MVT::ValueType in a struct to get type safety	2008-06-06 12:08:01 +00:00
AlphaISelLowering.cpp	Wrap MVT::ValueType in a struct to get type safety	2008-06-06 12:08:01 +00:00
AlphaISelLowering.h	Wrap MVT::ValueType in a struct to get type safety	2008-06-06 12:08:01 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp
AlphaRegisterInfo.cpp
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp
AlphaTargetAsmInfo.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h	Change target-specific classes to use more precise static types.	2008-05-14 01:58:56 +00:00
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html