Eli Friedman 84a6126937 Add missing includes/decls. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143722 91177308-0d34-0410-b5e6-96231b3b80d8		2011-11-04 18:45:34 +00:00
..
Mangler.h
Target.td	Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.	2011-10-18 19:18:52 +00:00
TargetCallingConv.h	Add missing includes/decls.	2011-11-04 18:45:34 +00:00
TargetCallingConv.td
TargetData.h	Haven't yet found a nice way to handle TargetData verification in the	2011-10-20 19:24:44 +00:00
TargetELFWriterInfo.h
TargetFrameLowering.h	Emit segmented-stack specific code into function prologues for	2011-08-30 19:39:58 +00:00
TargetInstrInfo.h	Expand the x86 V_SET0* pseudos right after register allocation.	2011-09-29 05:10:54 +00:00
TargetIntrinsicInfo.h	land David Blaikie's patch to de-constify Type, with a few tweaks.	2011-07-18 04:54:35 +00:00
TargetJITInfo.h
TargetLibraryInfo.h	add a copy ctor to TargetLibraryInfo.	2011-05-21 20:09:13 +00:00
TargetLowering.h	Rename NonScalarIntSafe to something more appropriate.	2011-10-26 23:50:43 +00:00
TargetLoweringObjectFile.h	Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.	2011-07-20 19:50:42 +00:00
TargetMachine.h	Delete the Latency scheduling preference.	2011-10-24 17:56:48 +00:00
TargetOpcodes.h	Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.	2011-06-16 18:17:13 +00:00
TargetOptions.h	Add missing includes/decls.	2011-11-04 18:45:34 +00:00
TargetRegisterInfo.h	Remove the TRI::getSubRegisterRegClass() hook.	2011-10-06 00:08:27 +00:00
TargetSchedule.td
TargetSelectionDAG.td	CR fixes per Bruno's request.	2011-09-11 15:02:23 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h	Rename TargetSubtarget to TargetSubtargetInfo for consistency.	2011-07-01 21:01:15 +00:00