Johnny Chen 857b1939da Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that ... all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-01 22:32:51 +00:00
..
arm-tests.txt	Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that	2011-04-01 22:32:51 +00:00
dg.exp
invalid-CPS2p-arm.txt	Also need to handle invalid imod values for CPS2p.	2011-03-25 17:03:12 +00:00
invalid-CPS3p-arm.txt	Plug a leak in the arm disassembler and put the tests back.	2011-03-24 21:14:28 +00:00
invalid-LDC-form-arm.txt	Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which	2011-03-31 20:54:30 +00:00
invalid-LDRrs-arm.txt	Fix single word and unsigned byte data transfer instruction encodings so that	2011-03-31 19:28:35 +00:00
invalid-LDRT-arm.txt	Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction	2011-04-01 20:21:38 +00:00
invalid-VLDMSDB_UPD-arm.txt	Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.	2011-03-29 19:10:06 +00:00
neon-tests.txt	Handle the added VBICiv*i* NEON instructions, too.	2011-03-24 22:04:39 +00:00
thumb-printf.txt	Add a thumb test file for printf (iOS 4.3).	2011-03-29 21:09:30 +00:00
thumb-tests.txt	Add a test case for thumb stc2 instruction.	2011-03-30 01:02:06 +00:00