Evan Cheng 8787c5f24e Add a if-conversion optimization that allows 'true' side of a diamond to be ... unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914 91177308-0d34-0410-b5e6-96231b3b80d8		2011-12-19 22:01:30 +00:00
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Analysis	Allow inlining of functions with returns_twice calls, if they have the	2011-12-18 20:35:43 +00:00
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AsmParser
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CodeGen	Add a if-conversion optimization that allows 'true' side of a diamond to be	2011-12-19 22:01:30 +00:00
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TableGen
Target	Add patterns for matching immediates whose lower 16-bit is cleared. These	2011-12-19 20:21:18 +00:00
Transforms	- Use getExitingBlock instead of getExitingBlocks.	2011-12-18 21:52:30 +00:00
VMCore
CMakeLists.txt
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