Evan Cheng d10eab0a95 Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte ... aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164089 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-18 01:42:45 +00:00
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ARM	Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte	2012-09-18 01:42:45 +00:00
CellSPU
CPP
Generic
Hexagon
MBlaze
Mips	Handled unaligned load/stores properly in Mips16	2012-09-15 01:02:03 +00:00
MSP430
NVPTX
PowerPC	This patch corrects logic in PPCFrameLowering for save and restore of	2012-09-12 14:47:47 +00:00
SPARC
Thumb
Thumb2	Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte	2012-09-18 01:42:45 +00:00
X86	Add some cases to x86 OptimizeCompare to handle DEC and INC, too.	2012-09-17 22:04:23 +00:00
XCore