Pranav Bhandarkar 02d937d864 Hexagon - Add peephole optimizations for zero extends. ... * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-02 20:22:51 +00:00
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Analysis	TBAA: remove !tbaa from testing cases if not used.	2013-04-29 22:42:01 +00:00
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BugPoint
CodeGen	Hexagon - Add peephole optimizations for zero extends.	2013-05-02 20:22:51 +00:00
DebugInfo	TBAA: remove !tbaa from testing cases if not used.	2013-05-02 18:11:35 +00:00
ExecutionEngine	Fix Addend computation for non external relocations on Macho.	2013-04-30 15:40:54 +00:00
Feature
FileCheck	Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.	2013-04-25 21:31:34 +00:00
Instrumentation
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MC	[mips] Test for r179873.	2013-04-30 20:48:49 +00:00
Object	Add missing ':'.	2013-04-26 17:54:46 +00:00
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TableGen
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Transforms	TBAA: remove !tbaa from testing cases if not used.	2013-05-02 18:11:35 +00:00
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