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llvm-6502/test/CodeGen
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Pranav Bhandarkar 02d937d864 Hexagon - Add peephole optimizations for zero extends. 
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 20:22:51 +00:00
..
AArch64
ARM Optimize away nop CONCAT_VECTOR nodes. 2013-05-01 19:18:51 +00:00
CPP
Generic TBAA: remove !tbaa from testing cases if not used. 2013-04-30 17:52:57 +00:00
Hexagon Hexagon - Add peephole optimizations for zero extends. 2013-05-02 20:22:51 +00:00
Inputs
MBlaze
Mips [mips] Fix handling of instructions which copy to/from accumulator registers. 2013-04-30 23:22:09 +00:00
MSP430
NVPTX
PowerPC LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
R600 TBAA: remove !tbaa from testing cases if not used. 2013-04-30 17:52:57 +00:00
SI
SPARC
Thumb LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
Thumb2 TBAA: remove !tbaa from testing cases if not used. 2013-04-30 17:52:57 +00:00
X86 TBAA: remove !tbaa from testing cases if not used. 2013-05-02 18:11:35 +00:00
XCore