llvm-6502/test/CodeGen
Bill Wendling 8a65e11c9f This testcase tests command line attributes which we don't yet support.
In fact, we're probably going to support these flags in completely different
ways. So this test is no longer valid.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182899 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30 00:32:04 +00:00
..
AArch64 Teach ReMaterialization to be more cunning about subregisters 2013-05-29 19:32:06 +00:00
ARM Order CALLSEQ_START and CALLSEQ_END nodes. 2013-05-29 22:03:55 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips Track IR ordering of SelectionDAG nodes 4/4. 2013-05-25 03:26:51 +00:00
MSP430
NVPTX
PowerPC Prefer to duplicate PPC Altivec loads when expanding unaligned loads 2013-05-26 18:08:30 +00:00
R600 R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 2013-05-23 18:26:42 +00:00
SI
SPARC [Sparc] Add support for leaf functions in sparc backend. 2013-05-29 04:46:31 +00:00
SystemZ [SystemZ] Two tests missing from previous commit 2013-05-29 11:59:26 +00:00
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X86 This testcase tests command line attributes which we don't yet support. 2013-05-30 00:32:04 +00:00
XCore