llvm-6502/lib/Target/Sparc
Dan Gohman da8ac5fd91 Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-03 16:55:19 +00:00
..
CMakeLists.txt CMake: Builds all targets. 2008-09-26 04:40:32 +00:00
DelaySlotFiller.cpp Tidy up several unbeseeming casts from pointer to intptr_t. 2008-09-04 17:05:41 +00:00
FPMover.cpp Tidy up several unbeseeming casts from pointer to intptr_t. 2008-09-04 17:05:41 +00:00
Makefile
README.txt
Sparc.h Avoid creating two TargetLowering objects for each target. 2008-10-03 16:55:19 +00:00
Sparc.td
SparcAsmPrinter.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
SparcInstrInfo.h Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested 2008-08-26 18:03:31 +00:00
SparcInstrInfo.td Rename ConstantSDNode::getValue to getZExtValue, for consistency 2008-09-12 16:56:44 +00:00
SparcISelDAGToDAG.cpp Avoid creating two TargetLowering objects for each target. 2008-10-03 16:55:19 +00:00
SparcISelLowering.cpp Make log, log2, log10, exp, exp2 use Expand by 2008-09-22 21:57:32 +00:00
SparcISelLowering.h Fix these enums' starting values to reflect the way that 2008-09-23 18:42:32 +00:00
SparcRegisterInfo.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetAsmInfo.cpp Add interface for section override. Use this for Sparc, since it should use named BSS section. 2008-08-16 12:58:12 +00:00
SparcTargetAsmInfo.h Reduce heap trashing due to std::string construction / concatenation via caching of section flags string representations 2008-08-16 12:57:07 +00:00
SparcTargetMachine.cpp Avoid creating two TargetLowering objects for each target. 2008-10-03 16:55:19 +00:00
SparcTargetMachine.h Avoid creating two TargetLowering objects for each target. 2008-10-03 16:55:19 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots