llvm-6502/test/MC
Asiri Rathnayake b0d513e1eb ARM: Fix another regression introduced in r223113
The changes in r223113 (ARM modified-immediate syntax) have broken
instructions like:
  mov r0, #~0xffffff00
The problem is that I've added a spurious range check on the immediate
operand to ensure that it lies between INT32_MIN and UINT32_MAX. While
this range check is correct in theory, it causes problems because the
operand is stored in an int64_t (by MC). So valid 32-bit constants like
\#~0xffffff00 become out of range. The solution is to simply remove this
range check. It is not possible to validate the range of the immediate
operand with the current setup because: 1) The operand is stored in an
int64_t by MC, 2) The immediate can be of the forms #imm, #-imm, #~imm
or even #((~imm)) etc. So we just chop the value to 32 bits and use it.

Also noted that the original range check was note tested by any of the
unit tests. I've added a new test to cover #~imm kind of operands.

Change-Id: I411e90d84312a2eff01b732bb238af536c4a7599

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228920 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-12 13:37:28 +00:00
..
AArch64 Fix some unnoticed/unwanted behavior change from r222319. 2015-02-04 03:10:03 +00:00
ARM ARM: Fix another regression introduced in r223113 2015-02-12 13:37:28 +00:00
AsmParser MC: Don't emit .no_dead_strip on targets which don't support it 2014-12-24 04:11:42 +00:00
COFF MC, COFF: Align section contents to a four byte boundary 2015-02-11 22:22:30 +00:00
Disassembler [mips] Merge disassemblers into a single implementation. 2015-02-11 11:28:56 +00:00
ELF Revert llvm/test/MC/ELF/noexec.s in r227074, "Fix a problem where the AArch64 ELF assembler was failing with" 2015-01-26 09:30:29 +00:00
Hexagon
MachO Add r224985 back with fixes. 2015-01-19 21:11:14 +00:00
Markup
Mips [mips][microMIPS] Implement movep instruction 2015-02-10 16:36:20 +00:00
PowerPC [PowerPC] Support the (old) cntlz instruction alias 2015-02-10 18:45:02 +00:00
R600 R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
Sparc
SystemZ
X86 [X86] Add GETSEC instruction. 2015-02-07 23:36:36 +00:00