Jim Grosbach 90502888f2 Update test for 139243 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139244 91177308-0d34-0410-b5e6-96231b3b80d8		2011-09-07 18:40:06 +00:00
..
arm-tests.txt	STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.	2011-08-18 22:47:44 +00:00
basic-arm-instructions.txt	Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.	2011-08-26 23:32:08 +00:00
dg.exp
fp-encoding.txt	Add some more comprehensive VFP decoding tests.	2011-08-15 21:29:01 +00:00
invalid-Bcc-thumb.txt
invalid-BFI-arm.txt
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt	Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.	2011-08-18 22:11:02 +00:00
invalid-DMB-thumb.txt
invalid-DSB-arm.txt
invalid-IT-thumb.txt	Add a testcase for r138625.	2011-08-26 06:45:08 +00:00
invalid-LDC-form-arm.txt
invalid-LDR_POST-arm.txt
invalid-LDR_PRE-arm.txt	invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.	2011-08-26 20:43:14 +00:00
invalid-LDRB_POST-arm.txt	Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.	2011-08-17 17:44:15 +00:00
invalid-LDRD_PRE-thumb.txt
invalid-LDRD-arm.txt	Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.	2011-08-18 18:03:02 +00:00
invalid-LDRrs-arm.txt
invalid-LDRT-arm.txt
invalid-LSL-regform.txt
invalid-MCR-arm.txt
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt
invalid-MSRi-arm.txt
invalid-RFEorLDMIA-arm.txt
invalid-RSC-arm.txt
invalid-SBFX-arm.txt
invalid-SMLAD-arm.txt
invalid-SRS-arm.txt
invalid-SSAT-arm.txt
invalid-STMIA_UPD-thumb.txt
invalid-STRBrs-arm.txt
invalid-SXTB-arm.txt
invalid-t2Bcc-thumb.txt
invalid-t2LDRBT-thumb.txt
invalid-t2LDREXD-thumb.txt
invalid-t2LDRSHi8-thumb.txt
invalid-t2LDRSHi12-thumb.txt
invalid-t2STR_POST-thumb.txt
invalid-t2STRD_PRE-thumb.txt
invalid-t2STREXB-thumb.txt
invalid-t2STREXD-thumb.txt
invalid-UMAAL-arm.txt
invalid-UQADD8-arm.txt
invalid-VLD1DUPq8_UPD-arm.txt
invalid-VLD3DUPd32_UPD-thumb.txt
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt
invalid-VST2b32_UPD-arm.txt
memory-arm-instructions.txt	Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.	2011-08-15 20:51:32 +00:00
neon-tests.txt
neon.txt	Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.	2011-08-22 21:34:00 +00:00
neont2.txt	Add a test file for Thumb2 NEON.	2011-08-15 23:42:20 +00:00
thumb1.txt	Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.	2011-08-26 18:09:22 +00:00
thumb2.txt	Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.	2011-09-07 17:55:19 +00:00
thumb-printf.txt
thumb-tests.txt	Update test for 139243	2011-09-07 18:40:06 +00:00