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https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
1.5 KiB
LLVM
52 lines
1.5 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
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; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
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define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
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; CHECK: v8i8
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %ret
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}
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define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: v4i16:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i16> %ret
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}
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define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
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; CHECK-LABEL: v2i32:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
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ret <2 x i32> %ret
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}
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define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
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; CHECK-LABEL: v1i64:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
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ret <1 x i64> %ret
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}
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define <2 x float> @v2f32(<4 x float> %a) nounwind {
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; CHECK-LABEL: v2f32:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3>
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ret <2 x float> %ret
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}
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define <1 x double> @v1f64(<2 x double> %a) nounwind {
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; CHECK-LABEL: v1f64:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1>
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ret <1 x double> %ret
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}
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