Chad Rosier 92bcd96bbc When pattern matching during instruction selection make sure shl x,1 is not ... converted to add x,x if x is a undef. add undef, undef does not guarantee that the resulting low order bit is zero. Fixes <rdar://problem/9453156> and <rdar://problem/9487392>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133022 91177308-0d34-0410-b5e6-96231b3b80d8		2011-06-14 22:29:10 +00:00
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Alpha
ARM	Since ARM's prefetch implementation predicted the presence of a instruction	2011-06-14 05:11:46 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic	Move the legalizer tests to the X86 directory because the test uses the x86	2011-06-07 05:23:58 +00:00
MBlaze
Mips	Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.	2011-06-09 16:03:19 +00:00
MSP430
PowerPC	Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.	2011-06-03 15:47:49 +00:00
PTX	PTX: add flag to disable mad/fma selection	2011-05-18 15:42:23 +00:00
SPARC
SystemZ
Thumb	Move this test to CodeGen/Thumb. rdar://problem/9416774	2011-05-11 19:41:28 +00:00
Thumb2	Implement Jakob's suggestion on how to detect fall thought without calling	2011-06-14 06:08:32 +00:00
X86	When pattern matching during instruction selection make sure shl x,1 is not	2011-06-14 22:29:10 +00:00
XCore	Add XCore intrinsic for crc8.	2011-05-31 16:24:49 +00:00