Chad Rosier 92bcd96bbc When pattern matching during instruction selection make sure shl x,1 is not
converted to add x,x if x is a undef.  add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 22:29:10 +00:00
..
2011-04-15 00:32:41 +00:00
2011-03-11 21:52:04 +00:00
2011-03-09 22:07:31 +00:00
2011-03-08 20:19:10 +00:00
2011-05-26 18:00:32 +00:00
2011-04-25 10:12:01 +00:00
2011-04-17 02:36:27 +00:00
2011-03-23 23:11:02 +00:00
2011-03-11 21:52:04 +00:00
2011-04-05 00:32:44 +00:00
2011-04-05 00:32:44 +00:00
2011-06-02 20:02:48 +00:00
2011-03-23 23:11:02 +00:00
2011-04-05 00:32:44 +00:00
2011-06-14 22:24:32 +00:00
2011-03-11 21:52:04 +00:00