Kai Nacke 92e28620d3 [mips] Refine octeon instructions seq/seqi/sne/snei ... This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225968 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-14 10:19:09 +00:00
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AArch64
ARM	ARM: add test for crc32 instructions in CodeGen.	2015-01-14 01:43:33 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Refine octeon instructions seq/seqi/sne/snei	2015-01-14 10:19:09 +00:00
MSP430
NVPTX
PowerPC	Revert "Insert random noops to increase security against ROP attacks (llvm)"	2015-01-14 05:24:33 +00:00
R600	R600/SI: Remove some redudant load testcases.	2015-01-14 01:35:26 +00:00
SPARC	Use the integrated assembler by default on SPARC.	2015-01-14 07:53:39 +00:00
SystemZ
Thumb
Thumb2
X86	Revert "Insert random noops to increase security against ROP attacks (llvm)"	2015-01-14 05:24:33 +00:00
XCore