6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 19:29:31 +00:00
Code Issues Projects Releases Wiki Activity
95971c51b0
llvm-6502/lib/Target/ARM
History
Jim Laskey 563321a258 Separate target specific asm properties from the asm printers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30126 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-06 18:34:40 +00:00
..
.cvsignore Ignore generated files 2006-05-27 01:23:30 +00:00
ARM.h add more condition codes 2006-09-02 20:24:25 +00:00
ARM.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
ARMAsmPrinter.cpp Separate target specific asm properties from the asm printers. 2006-09-06 18:34:40 +00:00
ARMFrameInfo.h use @ for comments 2006-08-25 17:55:16 +00:00
ARMInstrInfo.cpp change the addressing mode of the str instruction to reg+imm 2006-08-08 20:35:03 +00:00
ARMInstrInfo.h change the addressing mode of the str instruction to reg+imm 2006-08-08 20:35:03 +00:00
ARMInstrInfo.td add the orr instruction 2006-09-06 18:03:12 +00:00
ARMISelDAGToDAG.cpp add support for returning 64bit values 2006-09-04 19:05:01 +00:00
ARMRegisterInfo.cpp Completely eliminate def&use operands. Now a register operand is EITHER a 2006-09-05 02:31:13 +00:00
ARMRegisterInfo.h getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
ARMRegisterInfo.td Constify some methods. Patch provided by Anton Vayvod, thanks! 2006-08-17 22:00:08 +00:00
ARMTargetMachine.cpp Completely rearchitect the interface between targets and the pass manager. 2006-09-04 04:14:57 +00:00
ARMTargetMachine.h Completely rearchitect the interface between targets and the pass manager. 2006-09-04 04:14:57 +00:00
Makefile added a skeleton of the ARM backend 2006-05-14 22:18:28 +00:00
README.txt add a README.txt 2006-08-22 12:22:46 +00:00

README.txt 

//===---------------------------------------------------------------------===//
// Random ideas for the ARM backend.
//===---------------------------------------------------------------------===//

Consider implementing a select with two conditional moves:

cmp x, y
moveq dst, a
movne dst, b