Evan Cheng 977679d603 Added a late machine instruction copy propagation pass. This catches ... opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8		2012-01-07 03:02:36 +00:00
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ARM	Added a late machine instruction copy propagation pass. This catches	2012-01-07 03:02:36 +00:00
CBackend
CellSPU
CPP
Generic	Manually upgrade the test suite to specify the flag to cttz and ctlz.	2011-12-12 11:59:10 +00:00
Hexagon	Hexagon: Fix a nasty order-of-initialization bug.	2011-12-16 19:08:59 +00:00
MBlaze
Mips	Have getRegForInlineAsmConstraint return the correct register class when target	2012-01-04 02:45:01 +00:00
MSP430
PowerPC	Cleanup stack/frame register define/kill states. This fixes two bugs:	2011-12-30 00:34:00 +00:00
PTX	PTX: Continue to fix up the register mess.	2011-12-06 17:39:48 +00:00
SPARC	Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since	2011-12-03 21:24:48 +00:00
Thumb	Fix more places which should be checking for iOS, not darwin.	2012-01-04 01:55:04 +00:00
Thumb2	Enable aligned NEON spilling by default.	2012-01-06 22:19:37 +00:00
X86	Added a late machine instruction copy propagation pass. This catches	2012-01-07 03:02:36 +00:00
XCore	FileCheck hygiene.	2012-01-05 00:43:34 +00:00