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mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
llvm-6502/lib/CodeGen
2013-08-26 23:24:31 +00:00
..
AsmPrinter Only emit the section sym if we're emitting the section. 2013-08-26 23:24:31 +00:00
SelectionDAG SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy() 2013-08-26 15:06:10 +00:00
AggressiveAntiDepBreaker.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Assert that the target provided hints are in the allocation order. 2013-02-19 18:41:01 +00:00
AllocationOrder.h
Analysis.cpp [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall. 2013-08-20 08:36:50 +00:00
AntiDepBreaker.h
BasicTargetTransformInfo.cpp Turn MipsOptimizeMathLibCalls into a target-independent scalar transform 2013-08-23 10:27:02 +00:00
BranchFolding.cpp Fix tail merging to assign the (more) correct BasicBlock when splitting. 2013-06-24 01:55:01 +00:00
BranchFolding.h [branchfolding] Fix typo in C++ editor declaration. 2013-08-12 20:49:27 +00:00
CalcSpillWeights.cpp Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
CallingConvLower.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
CMakeLists.txt Remove the old CodePlacementOpt pass. 2013-03-29 17:14:24 +00:00
CodeGen.cpp This patch breaks up Wrap.h so that it does not have to include all of 2013-05-01 20:59:00 +00:00
CriticalAntiDepBreaker.cpp Use SmallVectorImpl instead of SmallVector as method argument to avoid specifying vector size. 2013-07-03 05:16:59 +00:00
CriticalAntiDepBreaker.h Use SmallVectorImpl instead of SmallVector as method argument to avoid specifying vector size. 2013-07-03 05:16:59 +00:00
DeadMachineInstructionElim.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
DFAPacketizer.cpp mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count. 2013-08-23 17:48:33 +00:00
DwarfEHPrepare.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
EarlyIfConversion.cpp Allow MachineTraceMetrics to be used when the model has no resources. 2013-04-02 22:27:45 +00:00
EdgeBundles.cpp
ErlangGC.cpp Add a GC plugin for Erlang 2013-03-25 13:47:46 +00:00
ExecutionDepsFix.cpp Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily. 2013-07-03 05:11:49 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp Re-apply r175688, with the changes suggested by Jakob in PR15320. 2013-02-21 22:16:43 +00:00
GCMetadata.cpp Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris. 2013-02-19 16:51:44 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp Fix a bug in IfConverter with nested predicates. 2013-07-24 20:20:37 +00:00
InlineSpiller.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
InterferenceCache.cpp
InterferenceCache.h
IntrinsicLowering.cpp Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 2013-05-21 14:37:16 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp typo. 2013-07-25 17:52:30 +00:00
LiveDebugVariables.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
LiveDebugVariables.h Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
LiveInterval.cpp Remove unnecessary parameter to RenumberValues. 2013-08-14 17:28:52 +00:00
LiveIntervalAnalysis.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
LiveIntervalUnion.cpp
LiveRangeCalc.cpp Copy single reaching defs directly into the LiveInterval. 2013-02-20 23:08:26 +00:00
LiveRangeCalc.h Remove declaration of nonexistant function. 2013-08-14 17:28:44 +00:00
LiveRangeEdit.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
LiveRegMatrix.cpp
LiveStackAnalysis.cpp
LiveVariables.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-11 16:22:38 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
LocalStackSlotAllocation.cpp LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
MachineBasicBlock.cpp Live-in copies go *after* EH_LABELs. 2013-07-04 04:32:35 +00:00
MachineBlockFrequencyInfo.cpp BlockFrequency: Bump up the entry frequency a bit. 2013-06-25 13:34:40 +00:00
MachineBlockPlacement.cpp Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by about 30% 2013-06-04 01:00:57 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
MachineCSE.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
MachineDominators.cpp
MachineFunction.cpp Use function attributes to indicate that we don't want to realign the stack. 2013-08-01 21:42:05 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Remove dead function. 2013-07-05 23:04:55 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp Fix overly pessimistic shortcut in post-RA MachineLICM 2013-08-20 09:11:13 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Use pointers to the MCAsmInfo and MCRegInfo. 2013-06-18 07:20:20 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegisterInfo.cpp Notify LiveRangeEdit of new virtual registers. 2013-08-14 23:50:09 +00:00
MachineScheduler.cpp Adds cyclic critical path computation and heuristics, temporarily disabled. 2013-08-23 17:48:43 +00:00
MachineSink.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
MachineSSAUpdater.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
MachineTraceMetrics.cpp Machine Model: Add MicroOpBufferSize and resource BufferSize. 2013-06-15 04:49:57 +00:00
MachineVerifier.cpp Add a wrapper for open. 2013-07-16 19:44:17 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Don't leak passes if added outside of the area determined by Started/Stopped flags. 2013-08-05 11:11:11 +00:00
PeepholeOptimizer.cpp
PHIElimination.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h Fixed another place in CodeGen where we had a typo in our editor C++ filetype declaration. 2013-08-12 20:52:06 +00:00
PostRASchedulerList.cpp mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count. 2013-08-23 17:48:33 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp PEI: Support for non-zero SPAdj at beginning of a basic block. 2013-07-15 23:47:29 +00:00
PrologEpilogInserter.h Added missing - in the header of PrologEpilogInserter.h so that editors properly realize it is a c++ header and not a c header. 2013-07-22 00:52:55 +00:00
PseudoSourceValue.cpp
README.txt Correct wrong register in this example, pointed out by Baoshan Pang. 2013-06-07 08:30:55 +00:00
RegAllocBase.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegAllocBase.h Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegAllocBasic.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegAllocFast.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
RegAllocGreedy.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegAllocPBQP.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegisterClassInfo.cpp MI-Sched: Adjust regpressure limits for reserved regs. 2013-06-21 18:32:58 +00:00
RegisterCoalescer.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Rename to RegPressure API parameters RegUnits. 2013-08-23 17:48:51 +00:00
RegisterScavenging.cpp RegScavenger should not exclude undef uses 2013-07-11 05:55:57 +00:00
ScheduleDAG.cpp Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily. 2013-07-03 05:11:49 +00:00
ScheduleDAGInstrs.cpp Adds cyclic critical path computation and heuristics, temporarily disabled. 2013-08-23 17:48:43 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
SjLjEHPrepare.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
SlotIndexes.cpp Make some fixes for LiveInterval repair with debug info. Debug value 2013-02-23 10:25:25 +00:00
Spiller.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
Spiller.h
SpillPlacement.cpp Reapply r185393. 2013-07-16 18:26:15 +00:00
SpillPlacement.h Remove floats from live range splitting costs. 2013-07-16 18:26:18 +00:00
SplitKit.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
SplitKit.h Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
StackColoring.cpp Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily. 2013-07-03 05:11:49 +00:00
StackProtector.cpp [stackprotector] Small cleanup. 2013-08-20 08:56:28 +00:00
StackSlotColoring.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
StrongPHIElimination.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
TailDuplication.cpp Fix build by replacing '>>' with '> >' 2013-07-14 06:12:01 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp Machine Model: Add MicroOpBufferSize and resource BufferSize. 2013-06-15 04:49:57 +00:00
TargetLoweringBase.cpp SelectionDAG: Use correct pointer size when lowering function arguments v2 2013-08-26 15:05:36 +00:00
TargetLoweringObjectFileImpl.cpp [-cxx-abi microsoft] Stick zero initialized symbols into the .bss section for COFF 2013-08-13 01:23:53 +00:00
TargetOptionsImpl.cpp Check only if we have this attribute. If it's not an attribute, then it's assumed false. 2013-08-22 21:16:14 +00:00
TargetRegisterInfo.cpp PrintVRegOrUnit 2013-08-23 17:48:53 +00:00
TargetSchedule.cpp MI-Sched: handle ReadAdvance latencies as used by Swift. 2013-06-17 21:45:18 +00:00
TwoAddressInstructionPass.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.