Devang Patel 9ac743a4ee Add dominance check for the instruction being hoisted. ... For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-10 19:09:20 +00:00
..
Analysis	Add an extra safety check in front of the optimization in r141442.	2011-10-08 02:16:39 +00:00
Archive
AsmParser	Remove last references to hotpatch.	2011-10-04 03:08:43 +00:00
Bitcode	Also update the EH with bitcode. I missed this earlier. Thanks to Duncan for pointing it out.	2011-10-05 07:04:14 +00:00
CodeGen	Add dominance check for the instruction being hoisted.	2011-10-10 19:09:20 +00:00
DebugInfo	lib/DebugInfo/DWARFDebugLine.cpp: De-Unicode-ify.	2011-10-08 11:22:47 +00:00
ExecutionEngine	MCJIT initialization TargetData	2011-09-30 16:40:10 +00:00
Linker
MC	MCAtom extending methods need to extend the range of the atom as well.	2011-10-10 18:09:38 +00:00
Object	lib/Object: Suppress warnings on gcc-4.3.4 cygwin	2011-10-08 11:22:53 +00:00
Support	The Mips specific function for instruction cache invalidation cannot be	2011-10-10 18:41:02 +00:00
TableGen	Revert r141079: tblgen: add preprocessor as a separate mode	2011-10-08 12:39:26 +00:00
Target	X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)	2011-10-10 18:34:56 +00:00
Transforms	LSR should only reuse phis that match its formula.	2011-10-07 23:46:21 +00:00
VMCore	Move default to top of switch	2011-10-07 16:27:01 +00:00
CMakeLists.txt	Move TableGen's parser and entry point into a library	2011-10-01 16:41:13 +00:00
Makefile