llvm-6502/lib/CodeGen
Matthias Braun 9e4654db1a Fix __builtin_setjmp in combination with sjlj exception handling.
llvm.eh.sjlj.setjmp was used as part of the SjLj exception handling
style but is also used in clang to implement __builtin_setjmp.  The ARM
backend needs to output additional dispatch tables for the SjLj
exception handling style, these tables however can't be emitted if
llvm.eh.sjlj.setjmp is simply used for __builtin_setjmp and no actual
landing pad blocks exist.

To solve this issue a new llvm.eh.sjlj.setup_dispatch intrinsic is
introduced which is used instead of llvm.eh.sjlj.setjmp in the SjLj
exception handling lowering, so we can differentiate between the case
where we actually need to setup a dispatch table and the case where we
just need the __builtin_setjmp semantic.

Differential Revision: http://reviews.llvm.org/D9313

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 22:34:16 +00:00
..
AsmPrinter Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
MIRParser MIR Serialization: Serialize the jump table index operands. 2015-07-15 23:38:35 +00:00
SelectionDAG Fix __builtin_setjmp in combination with sjlj exception handling. 2015-07-16 22:34:16 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
AllocationOrder.cpp TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
AllocationOrder.h TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
Analysis.cpp Make TargetLowering::getPointerTy() taking DataLayout as an argument 2015-07-09 02:09:04 +00:00
AntiDepBreaker.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
AtomicExpandPass.cpp
BasicTargetTransformInfo.cpp Make TargetTransformInfo keeping a reference to the Module DataLayout 2015-07-09 02:08:42 +00:00
BranchFolding.cpp
BranchFolding.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
CalcSpillWeights.cpp
CallingConvLower.cpp
CMakeLists.txt [InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics. 2015-06-26 02:10:27 +00:00
CodeGen.cpp
CodeGenPrepare.cpp Make isLegalAddressingMode() taking DataLayout as an argument 2015-07-09 02:09:40 +00:00
CoreCLRGC.cpp
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
DeadMachineInstructionElim.cpp Rename llvm.frameescape and llvm.framerecover to localescape and localrecover 2015-07-07 22:25:32 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp
EarlyIfConversion.cpp
EdgeBundles.cpp
ErlangGC.cpp
ExecutionDepsFix.cpp MachineRegisterInfo: Remove UsedPhysReg infrastructure 2015-07-14 17:52:07 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
FaultMaps.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCRootLowering.cpp
GCStrategy.cpp
GlobalMerge.cpp Redirect DataLayout from TargetMachine to Module in GlobalMerge 2015-07-07 18:49:25 +00:00
IfConversion.cpp
ImplicitNullChecks.cpp [ImplicitNullChecks] Fix a memory leak. 2015-07-09 20:13:31 +00:00
InlineSpiller.cpp
InterferenceCache.cpp
InterferenceCache.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
InterleavedAccessPass.cpp [InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on windows. 2015-06-26 04:38:21 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp
LiveDebugVariables.cpp
LiveDebugVariables.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
LiveInterval.cpp LiveInterval: Document and enforce rules about empty subranges. 2015-07-16 18:55:35 +00:00
LiveIntervalAnalysis.cpp LiveInterval: Document and enforce rules about empty subranges. 2015-07-16 18:55:35 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp LivePhysRegs: Add support to add pristine registers when populating with live-in/live-out registers. 2015-07-01 17:17:17 +00:00
LiveRangeCalc.cpp
LiveRangeCalc.h
LiveRangeEdit.cpp
LiveRegMatrix.cpp MachineRegisterInfo: Remove UsedPhysReg infrastructure 2015-07-14 17:52:07 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMBuild.txt
LLVMTargetMachine.cpp llc: Add a 'run-pass' option. 2015-07-06 17:44:26 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp CodeGen: Push the ModuleSlotTracker through MachineOperands 2015-06-26 22:06:47 +00:00
MachineBlockFrequencyInfo.cpp Rename doFunction() in BFI to calculate() and change its parameters from pointers to references. 2015-07-15 19:58:26 +00:00
MachineBlockPlacement.cpp Test commit. 2015-07-15 17:58:15 +00:00
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp [MachineCombiner] Work with itineraries 2015-07-15 08:22:23 +00:00
MachineCopyPropagation.cpp
MachineCSE.cpp
MachineDominanceFrontier.cpp
MachineDominators.cpp Remove macro guards for extern template instantiations. 2015-07-13 17:21:31 +00:00
MachineFunction.cpp Redirect DataLayout from TargetMachine to Module in MachineFunction 2015-07-07 18:20:57 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp CodeGen: Create a proper ModuleSlotTracker for MachineInstr 2015-06-26 23:18:44 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp
MachineLoopInfo.cpp Rename LoopInfo::Analyze() to LoopInfo::analyze() and turn its parameter type to const&. 2015-07-16 18:23:57 +00:00
MachineModuleInfo.cpp [CodeGen] Force emission of personality directive if explicitly specified 2015-07-14 19:22:51 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp MachineRegisterInfo: Remove UsedPhysReg infrastructure 2015-07-14 17:52:07 +00:00
MachineScheduler.cpp
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp use range-based for loops; NFCI 2015-07-06 16:27:35 +00:00
MachineVerifier.cpp LiveInterval: Document and enforce rules about empty subranges. 2015-07-16 18:55:35 +00:00
Makefile
MIRPrinter.cpp MIR Serialization: Serialize the jump table index operands. 2015-07-15 23:38:35 +00:00
MIRPrinter.h
MIRPrintingPass.cpp
module.modulemap
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Redirect DataLayout from TargetMachine to Module in SjLjEHPrepare 2015-07-08 01:00:31 +00:00
PeepholeOptimizer.cpp Revert "Refactor optimizeUncoalescable logic" 2015-07-15 18:10:46 +00:00
PHIElimination.cpp
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp MachineRegisterInfo: Remove UsedPhysReg infrastructure 2015-07-14 17:52:07 +00:00
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
RegAllocFast.cpp MachineRegisterInfo: Remove UsedPhysReg infrastructure 2015-07-14 17:52:07 +00:00
RegAllocGreedy.cpp TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
RegAllocPBQP.cpp
RegisterClassInfo.cpp
RegisterCoalescer.cpp RegisterCoalescer: Cleanup empty subranges after shrinkToUses() 2015-06-30 00:33:44 +00:00
RegisterCoalescer.h
RegisterPressure.cpp RegisterPressure: Add PressureDiff::dump() 2015-07-08 23:40:27 +00:00
RegisterScavenging.cpp
ScheduleDAG.cpp
ScheduleDAGInstrs.cpp Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
ShadowStackGCLowering.cpp
ShrinkWrap.cpp
SjLjEHPrepare.cpp Fix __builtin_setjmp in combination with sjlj exception handling. 2015-07-16 22:34:16 +00:00
SlotIndexes.cpp
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp
SplitKit.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
StackColoring.cpp
StackMapLivenessAnalysis.cpp [StackMap Liveness] Calling the base class' getAnalysisUsage method. NFCI. 2015-07-07 02:05:18 +00:00
StackMaps.cpp Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
StackProtector.cpp Redirect DataLayout from TargetMachine to Module in StackProtector 2015-07-07 23:38:49 +00:00
StackSlotColoring.cpp
StatepointExampleGC.cpp
TailDuplication.cpp
TargetFrameLoweringImpl.cpp PrologEpilogInserter: Rewrite API to determine callee save regsiters. 2015-07-14 17:17:13 +00:00
TargetInstrInfo.cpp Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
TargetLoweringBase.cpp [Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute difference operation 2015-07-16 15:22:46 +00:00
TargetLoweringObjectFileImpl.cpp Remove DataLayout from TargetLoweringObjectFile, redirect to Module 2015-07-16 06:04:17 +00:00
TargetOptionsImpl.cpp Use function attribute "trap-func-name" and remove TargetOptions::TrapFuncName. 2015-07-02 22:13:27 +00:00
TargetRegisterInfo.cpp TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
TargetSchedule.cpp
TwoAddressInstructionPass.cpp [TwoAddressInstructionPass] Rename a variable to match the coding style. 2015-07-06 20:12:54 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp MachineRegisterInfo: Remove UsedPhysReg infrastructure 2015-07-14 17:52:07 +00:00
WinEHPrepare.cpp [SEH] Push reloads of the SEH code past phi nodes 2015-07-10 22:21:54 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.