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a1deca3cd6
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into: _test1: slwi r2, r4, 4 add r2, r2, r3 lwz r3, 36(r2) blr _test2: mulli r2, r4, 5 add r2, r2, r3 lbz r2, 11(r2) extsb r3, r2 blr instead of: _test1: addi r2, r4, 2 slwi r2, r2, 4 add r2, r3, r2 lwz r3, 4(r2) blr _test2: addi r2, r4, 2 mulli r2, r2, 5 add r2, r3, r2 lbz r2, 1(r2) extsb r3, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26535 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
DAGCombiner.cpp | ||
LegalizeDAG.cpp | ||
Makefile | ||
ScheduleDAG.cpp | ||
ScheduleDAGList.cpp | ||
ScheduleDAGSimple.cpp | ||
SelectionDAG.cpp | ||
SelectionDAGISel.cpp | ||
SelectionDAGPrinter.cpp | ||
TargetLowering.cpp |