Jyotsna Verma a29a8965e2 Hexagon: Pass to replace tranfer/copy instructions into combine instruction ... where possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-14 18:54:06 +00:00
..
AArch64	AArch64: support literal pool access in large memory model.	2013-05-04 16:54:07 +00:00
ARM	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
CPP
Generic	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	This is the first of three patches which creates stubs used for	2013-05-14 02:00:24 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX
PowerPC	PPC32: Fix stack collision between FP and CR save areas.	2013-05-14 16:08:32 +00:00
R600	R600/SI: Add lit test coverage for the remaining patterns added recently	2013-05-14 09:53:30 +00:00
SI
SPARC	Recognize sparc64 as an alias for sparcv9 triples.	2013-05-14 17:47:27 +00:00
SystemZ	[SystemZ] Add CodeGen test cases	2013-05-06 16:17:29 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
X86	Reapply "Subtract isn't commutative, fix this for MMX psub." with	2013-05-14 18:33:40 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00