Andrea Di Biagio a29b054e7a Added new X86 patterns to select SSE scalar fp arithmetic instructions from ... a vector packed single/double fp operation followed by a vector insert. The effect is that the backend coverts the packed fp instruction followed by a vectro insert into a SSE or AVX scalar fp instruction. For example, given the following code: __m128 foo(__m128 A, __m128 B) { __m128 C = A + B; return (__m128) {c[0], a[1], a[2], a[3]}; } previously we generated: addps %xmm0, %xmm1 movss %xmm1, %xmm0 we now generate: addss %xmm1, %xmm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197145 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-12 11:50:47 +00:00
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AArch64	[AArch64]Fix the problem that AArch64 backend fails to select scalar_to_vector of vector types having more than one element.	2013-12-12 07:36:26 +00:00
ARM	ARM: constrain register-class in fast-isel	2013-12-11 16:04:57 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.	2013-12-11 03:32:44 +00:00
MSP430
NVPTX	[NVPTX] Fix off-by-one error when creating the VT list for an SDNode	2013-12-05 12:58:00 +00:00
PowerPC	Improve instruction scheduling for the PPC POWER7	2013-12-12 00:19:11 +00:00
R600	R600/SI: Add i64 cmp tests	2013-12-10 21:11:55 +00:00
SPARC	[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.	2013-12-09 05:13:25 +00:00
SystemZ	[SystemZ] Optimize fcmp X, 0 in cases where X is also negated	2013-12-11 11:45:08 +00:00
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X86	Added new X86 patterns to select SSE scalar fp arithmetic instructions from	2013-12-12 11:50:47 +00:00
XCore