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a3635eefc7
llvm-6502/test/CodeGen/NVPTX
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Justin Holewinski a3635eefc7 [NVPTX] Fix bug in stack code generation causes by MC conversion 
We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187799 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 14:13:31 +00:00
..
add-128bit.ll [NVPTX] 64-bit ADDC/ADDE are not legal 2013-07-01 12:59:04 +00:00
annotations.ll [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway. 2013-03-30 14:29:30 +00:00
arithmetic-fp-sm20.ll
arithmetic-int.ll [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway. 2013-03-30 14:29:30 +00:00
calling-conv.ll [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway. 2013-03-30 14:29:30 +00:00
compare-int.ll [NVPTX] Calling conventions fix 2013-06-28 17:58:10 +00:00
convert-fp.ll [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway. 2013-03-30 14:29:30 +00:00
convert-int-sm20.ll [NVPTX] Calling conventions fix 2013-06-28 17:58:10 +00:00
ctlz.ll [NVPTX] Add support for cttz/ctlz/ctpop 2013-06-28 17:58:07 +00:00
ctpop.ll Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. 2013-07-13 20:38:47 +00:00
cttz.ll [NVPTX] Add support for cttz/ctlz/ctpop 2013-06-28 17:58:07 +00:00
fast-math.ll [NVPTX] Use approximate FP ops when unsafe-fp-math is used, and append 2013-07-22 12:18:04 +00:00
fma-disable.ll
fma.ll
fp-literals.ll [NVPTX] Start conversion to MC infrastructure 2013-08-06 14:13:27 +00:00
generic-to-nvvm.ll [NVPTX] Add support for selecting CUDA vs OCL mode based on triple 2013-06-21 18:51:49 +00:00
global-ordering.ll [NVPTX] Order global variables in def-use order before emiting them in the final assembly 2012-11-16 21:03:51 +00:00
i1-global.ll [NVPTX] Add support for selecting CUDA vs OCL mode based on triple 2013-06-21 18:51:49 +00:00
i1-param.ll [NVPTX] Add support for selecting CUDA vs OCL mode based on triple 2013-06-21 18:51:49 +00:00
i8-param.ll Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. 2013-07-13 20:38:47 +00:00
intrin-nocapture.ll [NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture is not valid in this case, and was causing incorrect optimizations. 2013-02-11 18:56:35 +00:00
intrinsic-old.ll [NVPTX] Re-enable support for virtual registers in the final output 2013-05-31 12:14:49 +00:00
intrinsics.ll [NVPTX] Re-enable support for virtual registers in the final output 2013-05-31 12:14:49 +00:00
ld-addrspace.ll [NVPTX] Calling conventions fix 2013-06-28 17:58:10 +00:00
ld-generic.ll [NVPTX] Calling conventions fix 2013-06-28 17:58:10 +00:00
ldu-i8.ll [NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value 2013-07-01 12:58:48 +00:00
ldu-reg-plus-offset.ll Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. 2013-07-13 20:38:47 +00:00
lit.local.cfg
load-sext-i1.ll [NVPTX] Add support for selecting CUDA vs OCL mode based on triple 2013-06-21 18:51:49 +00:00
local-stack-frame.ll [NVPTX] Fix bug in stack code generation causes by MC conversion 2013-08-06 14:13:31 +00:00
module-inline-asm.ll [NVPTX] Add support for module-scope inline asm 2013-07-01 13:00:14 +00:00
nvvm-reflect.ll [NVPTX] Add NVVMReflect pass to allow compile-time selection of 2013-03-30 14:29:25 +00:00
param-align.ll
pr13291-i1-store.ll [NVPTX] Clean up comparison/select/convert patterns and factor out PTX instructions from their patterns 2013-06-28 17:58:04 +00:00
pr16278.ll [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space 2013-06-10 13:29:47 +00:00
ptx-version-30.ll [NVPTX] Add more precise PTX/SM target attributes 2012-11-12 03:16:43 +00:00
ptx-version-31.ll [NVPTX] Add more precise PTX/SM target attributes 2012-11-12 03:16:43 +00:00
refl1.ll [NVPTX] Add support for selecting CUDA vs OCL mode based on triple 2013-06-21 18:51:49 +00:00
rsqrt.ll Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. 2013-07-13 20:38:47 +00:00
sched1.ll Propagate DAG node ordering during type legalization and instruction selection 2013-03-20 00:10:32 +00:00
sched2.ll Propagate DAG node ordering during type legalization and instruction selection 2013-03-20 00:10:32 +00:00
sext-in-reg.ll Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. 2013-07-13 20:38:47 +00:00
sext-params.ll [NVPTX] Handle signext/zeroext attributes properly 2013-07-01 12:58:58 +00:00
simple-call.ll
sm-version-20.ll [NVPTX] Add more precise PTX/SM target attributes 2012-11-12 03:16:43 +00:00
sm-version-21.ll [NVPTX] Add more precise PTX/SM target attributes 2012-11-12 03:16:43 +00:00
sm-version-30.ll [NVPTX] Add more precise PTX/SM target attributes 2012-11-12 03:16:43 +00:00
sm-version-35.ll [NVPTX] Add more precise PTX/SM target attributes 2012-11-12 03:16:43 +00:00
st-addrspace.ll [NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16. 2013-06-28 17:57:59 +00:00
st-generic.ll [NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16. 2013-06-28 17:57:59 +00:00
tuple-literal.ll [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway. 2013-03-30 14:29:30 +00:00
vec-param-load.ll [NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos 2013-07-01 12:59:01 +00:00
vector-args.ll [NVPTX] Add support for vectorized function return values 2013-06-28 17:57:55 +00:00
vector-compare.ll Allow targets to prefer TypeSplitVector over TypePromoteInteger when computing the legalization method for vectors 2012-11-29 14:26:24 +00:00
vector-loads.ll Propagate DAG node ordering during type legalization and instruction selection 2013-03-20 00:10:32 +00:00
vector-select.ll Teach the legalizer how to handle operands for VSELECT nodes 2012-11-29 14:26:28 +00:00
vector-stores.ll Add a target legalize hook for SplitVectorOperand (again) 2013-07-26 13:28:29 +00:00