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InstPrinter
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MCTargetDesc
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Completely rewrite ELFObjectWriter::RecordRelocation.
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2014-03-29 06:26:49 +00:00 |
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TargetInfo
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AMDGPU.h
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AMDGPU.td
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AMDGPUAsmPrinter.cpp
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
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AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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AMDGPUInstructions.td
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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AMDGPUIntrinsics.td
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R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
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2014-03-31 18:21:18 +00:00 |
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AMDGPUISelDAGToDAG.cpp
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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AMDGPUISelLowering.cpp
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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AMDGPUISelLowering.h
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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MachineInstr: introduce explicit_operands and implicit_operands ranges
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2014-04-05 22:42:04 +00:00 |
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AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
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Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
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2014-04-04 05:16:06 +00:00 |
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AMDGPURegisterInfo.h
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Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
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2014-04-04 05:16:06 +00:00 |
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AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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AMDGPUSubtarget.h
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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AMDGPUTargetMachine.cpp
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AMDGPUTargetMachine.h
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AMDGPUTargetTransformInfo.cpp
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Fix tabs
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2014-04-04 20:13:08 +00:00 |
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AMDILBase.td
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AMDILCFGStructurizer.cpp
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelLowering.cpp
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AMDILRegisterInfo.td
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CaymanInstructions.td
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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CMakeLists.txt
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EvergreenInstructions.td
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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LLVMBuild.txt
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Makefile
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Processors.td
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrFormats.td
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R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
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R600Intrinsics.td
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R600ISelLowering.cpp
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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R600ISelLowering.h
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R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
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2014-03-27 17:23:24 +00:00 |
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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SIDefines.h
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SIFixSGPRCopies.cpp
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R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
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2014-04-07 19:45:45 +00:00 |
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SIInsertWaits.cpp
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SIInstrFormats.td
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SIInstrInfo.cpp
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R600/SI: Match not instruction.
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2014-04-09 07:16:16 +00:00 |
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SIInstrInfo.h
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R600/SI: Implement shouldConvertConstantLoadToIntImm
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2014-03-31 19:54:27 +00:00 |
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SIInstrInfo.td
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R600/SI: Lower 64-bit immediates using REG_SEQUENCE
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2014-04-03 20:19:27 +00:00 |
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SIInstructions.td
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R600/SI: Match not instruction.
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2014-04-09 07:16:16 +00:00 |
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SIIntrinsics.td
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SIISelLowering.cpp
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R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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2014-04-07 19:45:41 +00:00 |
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SIISelLowering.h
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Change shouldSplitVectorElementType to better match the description.
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2014-03-31 20:54:58 +00:00 |
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SILowerControlFlow.cpp
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R600: avoid calling std::next on an iterator that might be end()
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2014-03-28 13:52:56 +00:00 |
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
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R600/SI: Return the correct index for VGPRs in getHWRegIndex()
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2014-03-31 14:01:52 +00:00 |
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SIRegisterInfo.h
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SIRegisterInfo.td
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SISchedule.td
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SITypeRewriter.cpp
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