Tim Northover aae0fa998a Teach ReMaterialization to be more cunning about subregisters ... This allows rematerialization during register coalescing to handle more cases involving operations like SUBREG_TO_REG which might need to be rematerialized using sub-register indices. For example, code like: v1(GPR64):sub_32 = MOVZ something v2(GPR64) = COPY v1(GPR64) should be convertable to: v2(GPR64):sub_32 = MOVZ something but previously we just gave up in places like this git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182872 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-29 19:32:06 +00:00
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AArch64	Teach ReMaterialization to be more cunning about subregisters	2013-05-29 19:32:06 +00:00
ARM	Track IR ordering of SelectionDAG nodes 4/4.	2013-05-25 03:26:51 +00:00
CPP
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon
Inputs
MBlaze
Mips	Track IR ordering of SelectionDAG nodes 4/4.	2013-05-25 03:26:51 +00:00
MSP430
NVPTX	[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic	2013-05-21 16:51:30 +00:00
PowerPC	Prefer to duplicate PPC Altivec loads when expanding unaligned loads	2013-05-26 18:08:30 +00:00
R600	R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg	2013-05-23 18:26:42 +00:00
SI
SPARC	[Sparc] Add support for leaf functions in sparc backend.	2013-05-29 04:46:31 +00:00
SystemZ	[SystemZ] Two tests missing from previous commit	2013-05-29 11:59:26 +00:00
Thumb
Thumb2
X86	Convert sqrt functions into sqrt instructions when -ffast-math is in effect.	2013-05-27 15:44:35 +00:00
XCore