Joerg Sonnenberger 4fd3d29275 Fix generation of the address size override prefix. Add assertions for ...

the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8

2012-03-21 05:48:07 +00:00

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3DNow.s

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2011-09-06-NoNewline.s

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address-size.s

Fix generation of the address size override prefix. Add assertions for

2012-03-21 05:48:07 +00:00

intel-syntax-2.s

Intel syntax. Support .intel_syntax directive.

2012-01-30 20:02:42 +00:00

intel-syntax-encoding.s

Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.

2012-01-30 22:47:12 +00:00

intel-syntax.s

Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]

2012-01-27 19:48:28 +00:00

lit.local.cfg

test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets.

2012-03-09 14:52:38 +00:00

padlock.s

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x86_64-avx-clmul-encoding.s

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x86_64-avx-encoding.s

Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.

2011-12-15 23:46:18 +00:00

x86_64-bmi-encoding.s

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x86_64-encoding.s

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x86_64-fma3-encoding.s

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x86_64-fma4-encoding.s

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x86_64-imm-widths.s

Replace a gross hack (the MOV64ri_alt instruction) with a slightly less

2010-10-05 21:09:45 +00:00

x86_64-xop-encoding.s

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x86_directives.s

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x86_errors.s

Added a missing error check for X86 assembly with mismatched base and index

2012-03-12 21:32:09 +00:00

x86_operands.s

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x86-32-avx.s

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x86-32-coverage.s

Add vmfunc instruction to X86 assembler and disassembler.

2012-02-19 01:39:49 +00:00

x86-32-fma3.s

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x86-32.s

Updated the llvm-mc disassembler C API to support for the X86 target.

2012-02-23 18:18:17 +00:00

x86-64.s

Change the X86 assembler to not require a segment register on string

2012-03-13 19:47:55 +00:00