llvm-6502/lib/Target/PowerPC
Nate Begeman ae1641c39f Match rotate. This does actually match the rotates in an rc5 cipher, but I
haven't seen it fire on our testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23863 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-21 06:36:18 +00:00
..
.cvsignore ignore generated files. 2004-11-21 00:00:54 +00:00
LICENSE.TXT Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I 2004-08-05 23:46:27 +00:00
Makefile Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td 2005-10-14 23:37:35 +00:00
PPC.h First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 2005-10-18 00:28:58 +00:00
PPC.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCAsmPrinter.cpp Fix the JIT encoding of LWA, LD, STD, and STDU. 2005-10-18 16:51:22 +00:00
PPCBranchSelector.cpp More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCCodeEmitter.cpp More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCFrameInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCInstrBuilder.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCInstrFormats.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCInstrInfo.cpp teach ppc backend these are copies 2005-10-19 01:50:36 +00:00
PPCInstrInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCInstrInfo.td Match rotate. This does actually match the rotates in an rc5 cipher, but I 2005-10-21 06:36:18 +00:00
PPCISelDAGToDAG.cpp Invert the TargetLowering flag that controls divide by consant expansion. 2005-10-21 00:02:42 +00:00
PPCISelLowering.cpp Invert the TargetLowering flag that controls divide by consant expansion. 2005-10-21 00:02:42 +00:00
PPCISelLowering.h Add the ability to lower return instructions to TargetLowering. This 2005-10-18 23:23:37 +00:00
PPCISelPattern.cpp Move the target constant divide optimization up into the dag combiner, so 2005-10-20 02:15:44 +00:00
PPCJITInfo.cpp More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCJITInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCRegisterInfo.cpp Fix the JIT encoding of LWA, LD, STD, and STDU. 2005-10-18 16:51:22 +00:00
PPCRegisterInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCRegisterInfo.td apply some tblgen majik to simplify the X register definitions 2005-10-19 00:17:55 +00:00
PPCRelocations.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCSchedule.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG3.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG4.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG4Plus.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG5.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCSubtarget.cpp Do the right thing and enable 64 bit regs under the control of a subtarget 2005-10-18 00:56:42 +00:00
PPCSubtarget.h Do the right thing and enable 64 bit regs under the control of a subtarget 2005-10-18 00:56:42 +00:00
PPCTargetMachine.cpp First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 2005-10-18 00:28:58 +00:00
PPCTargetMachine.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
README.txt add a case 2005-10-18 06:30:51 +00:00

TODO:
* gpr0 allocation
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* use stfiwx in float->int
* be able to combine sequences like the following into 2 instructions:
	lis r2, ha16(l2__ZTV4Cell)
	la r2, lo16(l2__ZTV4Cell)(r2)
	addi r2, r2, 8

* Teach LLVM how to codegen this:
unsigned short foo(float a) { return a; }
as:
_foo:
        fctiwz f0,f1
        stfd f0,-8(r1)
        lhz r3,-2(r1)
        blr
not:
_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

and:
  extern int X, Y; int* test(int C) { return C? &X : &Y; }
as one load when using --enable-pic.

* Support 'update' load/store instructions.  These are cracked on the G5, but
  are still a codesize win.

* Add a custom legalizer for the GlobalAddress node, to move the funky darwin
  stub stuff from the instruction selector to the legalizer (exposing low-level
  operations to the dag for optzn.  For example, we want to codegen this:

        int A = 0;
        void B() { A++; }
  as:
        lis r9,ha16(_A)
        lwz r2,lo16(_A)(r9)
        addi r2,r2,1
        stw r2,lo16(_A)(r9)
  not:
        lis r2, ha16(_A)
        lwz r2, lo16(_A)(r2)
        addi r2, r2, 1
        lis r3, ha16(_A)
        stw r2, lo16(_A)(r3)

* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

===-------------------------------------------------------------------------===

* Codegen this:

   void test2(int X) {
     if (X == 0x12345678) bar();
   }

    as:

       xoris r0,r3,0x1234
       cmpwi cr0,r0,0x5678
       beq cr0,L6

    not:

        lis r2, 4660
        ori r2, r2, 22136 
        cmpw cr0, r3, r2  
        bne .LBB_test2_2

===-------------------------------------------------------------------------===

Lump the constant pool for each function into ONE pic object, and reference
pieces of it as offsets from the start.  For functions like this (contrived
to have lots of constants obviously):

double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }

We generate:

_X:
        lis r2, ha16(.CPI_X_0)
        lfd f0, lo16(.CPI_X_0)(r2)
        lis r2, ha16(.CPI_X_1)
        lfd f2, lo16(.CPI_X_1)(r2)
        fmadd f0, f1, f0, f2
        lis r2, ha16(.CPI_X_2)
        lfd f1, lo16(.CPI_X_2)(r2)
        lis r2, ha16(.CPI_X_3)
        lfd f2, lo16(.CPI_X_3)(r2)
        fmadd f1, f0, f1, f2
        blr

It would be better to materialize .CPI_X into a register, then use immediates
off of the register to avoid the lis's.  This is even more important in PIC 
mode.

===-------------------------------------------------------------------------===

Implement Newton-Rhapson method for improving estimate instructions to the
correct accuracy, and implementing divide as multiply by reciprocal when it has
more than one use.  Itanium will want this too.

===-------------------------------------------------------------------------===

int foo(int a, int b) { return a == b ? 16 : 0; }
_foo:
        cmpw cr7, r3, r4
        mfcr r2
        rlwinm r2, r2, 31, 31, 31
        slwi r3, r2, 4
        blr

If we exposed the srl & mask ops after the MFCR that we are doing to select
the correct CR bit, then we could fold the slwi into the rlwinm before it.