Jingyue Wu 1d1d705a95 [NVPTX] aligned byte-buffers for vector return types ... Summary: Fixes PR21100 which is caused by inconsistency between the declared return type and the expected return type at the call site. The new behavior is consistent with nvcc and the NVPTXTargetLowering::getPrototype function. Test Plan: test/Codegen/NVPTX/vector-return.ll Reviewers: jholewinski Reviewed By: jholewinski Subscribers: llvm-commits, meheff, eliben, jholewinski Differential Revision: http://reviews.llvm.org/D5612 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220607 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-25 03:46:16 +00:00
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AArch64	[AArch64] Fix fast-isel of cbz of i1, i8, i16	2014-10-24 09:54:41 +00:00
ARM	Do not emit intermediate register for zero FP immediate	2014-10-23 15:31:50 +00:00
CPP
Generic	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Hexagon	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Inputs	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Mips	[mips] For N32/N64, structs must be passed in the upper bits of a register.	2014-10-24 13:09:19 +00:00
MSP430
NVPTX	[NVPTX] aligned byte-buffers for vector return types	2014-10-25 03:46:16 +00:00
PowerPC	[PATCH] Support select-cc for VSFRC when VSX is enabled	2014-10-22 16:58:20 +00:00
R600	R600/SI: Add another failing testcase for i1 copies	2014-10-22 05:30:42 +00:00
SPARC
SystemZ
Thumb	[Thumb] Fix crash in Thumb1RegisterInfo::rewriteFrameIndex	2014-10-20 11:00:18 +00:00
Thumb2	ARM: Fix a bug which was causing convergence failure in constant-island pass.	2014-10-17 01:31:47 +00:00
X86	[X86][SSE] Bitcast assertion in XFormVExtractWithShuffleIntoLoad	2014-10-24 21:04:41 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00