Hal Finkel 8cc3474f72 Add readcyclecounter lowering on PPC64. ... On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8		2012-08-04 14:10:46 +00:00
..
Mangler.h
Target.td	Remove support for 'CompositeIndices' and sub-register cycles.	2012-07-26 23:39:50 +00:00
TargetCallingConv.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameLowering.h
TargetInstrInfo.h	X86 Peephole: fold loads to the source register operand if possible.	2012-08-02 19:37:32 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TargetJITInfo.h
TargetLibraryInfo.h	Try to reduce the compile time impact of r161232.	2012-08-03 21:26:24 +00:00
TargetLowering.h	Fall back to selection DAG isel for calls to builtin functions.	2012-08-03 04:06:28 +00:00
TargetLoweringObjectFile.h
TargetMachine.h	Extend TargetPassConfig to allow running only a subset of the normal passes.	2012-07-02 19:48:45 +00:00
TargetOpcodes.h
TargetOptions.h	Target option DisableJumpTables is a gross hack. Move it to TargetLowering instead.	2012-07-02 22:39:56 +00:00
TargetRegisterInfo.h	Add TargetRegisterInfo::hasRegUnit().	2012-08-02 14:45:53 +00:00
TargetSchedule.td	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TargetSelectionDAG.td	Add readcyclecounter lowering on PPC64.	2012-08-04 14:10:46 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h