Bill Schmidt b34c79e4bb Fix PR15155: lost vadd/vsplat optimization. ... During lowering of a BUILD_VECTOR, we look for opportunities to use a vector splat. When the splatted value fits in 5 signed bits, a single splat does the job. When it doesn't fit in 5 bits but does fit in 6, and is an even value, we can splat on half the value and add the result to itself. This last optimization hasn't been working recently because of improved constant folding. To circumvent this, create a pseudo VADD_SPLAT that can be expanded during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175632 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-20 15:50:31 +00:00
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AArch64	AArch64: remove ConstantIsland pass & put literals in separate section.	2013-02-15 09:33:43 +00:00
ARM	ARM NEON: Merge a f32 bitcast of a v2i32 extractelt	2013-02-19 15:27:05 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Hexagon: add support for predicate-GPR copies.	2013-02-13 22:56:34 +00:00
MBlaze
Mips	Expand pseudos/macros:	2013-02-20 05:45:15 +00:00
MSP430	Add support for varargs functions for msp430.	2012-11-21 17:28:27 +00:00
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	Fix PR15155: lost vadd/vsplat optimization.	2013-02-20 15:50:31 +00:00
R600	R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern	2013-02-18 14:11:28 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Use TargetTransformInfo to control switch-to-lookup table transformation	2012-10-30 11:23:25 +00:00
Thumb	Fix thumbv5e frame lowering assertion failure.	2013-02-20 12:21:33 +00:00
Thumb2	ARM: Allocation hints must make sure to be in the alloc order.	2013-02-19 18:55:36 +00:00
X86	I optimized the following patterns:	2013-02-20 12:42:54 +00:00
XCore	Fix handling of aliases to functions.	2012-11-16 21:12:38 +00:00