Richard Barton b5523ce1bb Add AArch32 DCPS{1,2,3} and HLT instructions. ... These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-05 14:14:19 +00:00
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AArch64	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
ARM	Add AArch32 DCPS{1,2,3} and HLT instructions.	2013-09-05 14:14:19 +00:00
AsmParser	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
COFF	Fix wrong code offset for unwind code SET_FPREG.	2013-08-27 04:16:16 +00:00
Disassembler	Add AArch32 DCPS{1,2,3} and HLT instructions.	2013-09-05 14:14:19 +00:00
ELF	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
MachO	The darwin integrated assembler for X86 in 64-bit mode is not rejecting	2013-08-29 00:19:03 +00:00
Markup	MC: Simple example parser for MC assembly markup.	2012-10-31 23:24:13 +00:00
Mips	[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.	2013-08-28 00:55:15 +00:00
PowerPC	Given target assembler parsers a chance to handle variant expressions	2013-08-27 20:23:19 +00:00
SystemZ	[SystemZ] Add NC, OC and XC	2013-09-05 10:36:45 +00:00
X86	[ms-inline asm] Support offsets after segment registers	2013-08-27 21:56:17 +00:00