Chris Lattner b779580100 If a register operand comes from the variadic part of a node, don't ...

verify the register constraint matches what the instruction expects.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48205 91177308-0d34-0410-b5e6-96231b3b80d8

2008-03-11 00:59:28 +00:00

..

CallingConvLower.cpp

Increase ISD::ParamFlags to 64 bits. Increase the ByValSize

2008-03-10 02:17:22 +00:00

DAGCombiner.cpp

Somewhat better solution.

2008-03-10 19:58:22 +00:00

LegalizeDAG.cpp

More APInt-ification.

2008-03-11 00:11:06 +00:00

LegalizeTypes.cpp

LegalizeTypes support for EXTRACT_VECTOR_ELT. The

2008-02-27 13:34:40 +00:00

LegalizeTypes.h

LegalizeTypes support for EXTRACT_VECTOR_ELT. The

2008-02-27 13:34:40 +00:00

LegalizeTypesExpand.cpp

APInt-ify this.

2008-03-10 23:38:17 +00:00

LegalizeTypesPromote.cpp

Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's

2008-03-10 15:42:14 +00:00

LegalizeTypesScalarize.cpp

LegalizeTypes support for EXTRACT_VECTOR_ELT. The

2008-02-27 13:34:40 +00:00

LegalizeTypesSplit.cpp

Add a FIXME about the VECTOR_SHUFFLE evil hack.

2008-02-27 17:39:13 +00:00

Makefile

remove attribution from lib Makefiles.

2007-12-29 20:09:26 +00:00

ScheduleDAG.cpp

If a register operand comes from the variadic part of a node, don't

2008-03-11 00:59:28 +00:00

ScheduleDAGList.cpp

Rename MRegisterInfo to TargetRegisterInfo.

2008-02-10 18:45:23 +00:00

ScheduleDAGRRList.cpp

Rename isOperand() to isOperandOf() (and other similar methods). It always confuses me.

2008-03-04 00:41:45 +00:00

SelectionDAG.cpp

Teach SD some vector identities, allowing us to compile vec_set-9 into:

2008-03-08 23:43:36 +00:00

SelectionDAGISel.cpp

Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's

2008-03-10 15:42:14 +00:00

SelectionDAGPrinter.cpp

Final de-tabification.

2008-02-27 06:33:05 +00:00

TargetLowering.cpp

Implement more support for fp-to-i128 and i128-to-fp conversions.

2008-03-10 23:03:31 +00:00