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a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
AsmPrinter | ||
TargetInfo | ||
CellSDKIntrinsics.td | ||
CMakeLists.txt | ||
Makefile | ||
README.txt | ||
SPU64InstrInfo.td | ||
SPU128InstrInfo.td | ||
SPU.h | ||
SPU.td | ||
SPUCallingConv.td | ||
SPUFrameInfo.cpp | ||
SPUFrameInfo.h | ||
SPUHazardRecognizers.cpp | ||
SPUHazardRecognizers.h | ||
SPUInstrBuilder.h | ||
SPUInstrFormats.td | ||
SPUInstrInfo.cpp | ||
SPUInstrInfo.h | ||
SPUInstrInfo.td | ||
SPUISelDAGToDAG.cpp | ||
SPUISelLowering.cpp | ||
SPUISelLowering.h | ||
SPUMachineFunction.h | ||
SPUMathInstr.td | ||
SPUMCAsmInfo.cpp | ||
SPUMCAsmInfo.h | ||
SPUNodes.td | ||
SPUOperands.td | ||
SPURegisterInfo.cpp | ||
SPURegisterInfo.h | ||
SPURegisterInfo.td | ||
SPURegisterNames.h | ||
SPUSchedule.td | ||
SPUSubtarget.cpp | ||
SPUSubtarget.h | ||
SPUTargetMachine.cpp | ||
SPUTargetMachine.h |
//===- README.txt - Notes for improving CellSPU-specific code gen ---------===// This code was contributed by a team from the Computer Systems Research Department in The Aerospace Corporation: - Scott Michel (head bottle washer and much of the non-floating point instructions) - Mark Thomas (floating point instructions) - Michael AuYeung (intrinsics) - Chandler Carruth (LLVM expertise) - Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise) THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR OTHERWISE. IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR SUCH DAMAGES ARE FORESEEABLE. --------------------------------------------------------------------------- --WARNING--: --WARNING--: The CellSPU work is work-in-progress and "alpha" quality code. --WARNING--: If you are brave enough to try this code or help to hack on it, be sure to add 'spu' to configure's --enable-targets option, e.g.: ./configure <your_configure_flags_here> \ --enable-targets=x86,x86_64,powerpc,spu --------------------------------------------------------------------------- TODO: * Create a machine pass for performing dual-pipeline scheduling specifically for CellSPU, and insert branch prediction instructions as needed. * i32 instructions: * i32 division (work-in-progress) * i64 support (see i64operations.c test harness): * shifts and comparison operators: done * sign and zero extension: done * addition: done * subtraction: needed * multiplication: done * i128 support: * zero extension, any extension: done * sign extension: needed * arithmetic operators (add, sub, mul, div): needed * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed * or: done * f64 support * Comparison operators: SETOEQ unimplemented SETOGT unimplemented SETOGE unimplemented SETOLT unimplemented SETOLE unimplemented SETONE unimplemented SETO done (lowered) SETUO done (lowered) SETUEQ unimplemented SETUGT unimplemented SETUGE unimplemented SETULT unimplemented SETULE unimplemented SETUNE unimplemented * LLVM vector suport * VSETCC needs to be implemented. It's pretty straightforward to code, but needs implementation. * Intrinsics * spu.h instrinsics added but not tested. Need to have an operational llvm-spu-gcc in order to write a unit test harness. ===-------------------------------------------------------------------------===