llvm-6502/lib
2013-05-20 14:42:43 +00:00
..
Analysis isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also. 2013-05-18 19:30:37 +00:00
Archive
AsmParser Add ArrayRef constructor from None, and do the cleanups that this constructor enables 2013-05-05 00:40:33 +00:00
Bitcode Micro-optimization: don't shift an entire bitcode record over to get the code. 2013-05-10 22:17:10 +00:00
CodeGen Add LLVMContext argument to getSetCCResultType 2013-05-18 00:21:46 +00:00
DebugInfo libDebugInfo depends on libObject nowadays. 2013-05-09 13:48:26 +00:00
ExecutionEngine AArch64: make RuntimeDyld relocations idempotent 2013-05-19 15:39:03 +00:00
IR Remove duplicated comment 2013-05-18 00:24:09 +00:00
IRReader Measure time that IR parsing took as part of the -time-passes measurement. 2013-04-03 15:33:45 +00:00
Linker Fix a performance bug in the Linker. 2013-05-04 05:05:18 +00:00
MC Cleanup relocation sorting for ELF. 2013-05-15 18:22:01 +00:00
Object Convert obj2yaml to use yamlio. 2013-05-17 22:58:42 +00:00
Option
Support Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072> 2013-05-19 20:33:51 +00:00
TableGen
Target Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). 2013-05-20 14:42:43 +00:00
Transforms LoopVectorize: Handle single edge PHIs 2013-05-18 18:38:34 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile