Ahmed Bougacha bed2308186 Add a way to define the bit range covered by a SubRegIndex. ... NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-31 17:08:36 +00:00
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CostTable.h	Moving Cost Tables up to share with other targets	2013-01-24 23:01:00 +00:00
Mangler.h	Don't reach into the middle of TargetMachine and cache one of its ivars.	2013-05-29 20:37:19 +00:00
Target.td	Add a way to define the bit range covered by a SubRegIndex.	2013-05-31 17:08:36 +00:00
TargetCallingConv.h	Remove unused, undefined ArgFlagsTy::getArgFlagsString; add a comment about 'returned'	2013-04-21 18:05:20 +00:00
TargetCallingConv.td	Add TableGen support for callee saved registers.	2012-01-17 22:46:58 +00:00
TargetFrameLowering.h	Provide the register scavenger to processFunctionBeforeFrameFinalized	2013-03-14 20:33:40 +00:00
TargetInstrInfo.h	Add a comment to TargetInstrInfo about FoldImmediate	2013-04-06 19:30:20 +00:00
TargetIntrinsicInfo.h	Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.	2012-09-17 06:59:23 +00:00
TargetItinerary.td	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TargetJITInfo.h	Sort the #include lines for the include/... tree with the script.	2012-12-03 17:02:12 +00:00
TargetLibraryInfo.h	Convert sqrt functions into sqrt instructions when -ffast-math is in effect.	2013-05-27 15:44:35 +00:00
TargetLowering.h	Track IR ordering of SelectionDAG nodes 2/4.	2013-05-25 02:42:55 +00:00
TargetLoweringObjectFile.h	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
TargetMachine.h	Remove the MachineMove class.	2013-05-13 01:16:13 +00:00
TargetOpcodes.h	Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be	2012-09-06 09:17:37 +00:00
TargetOptions.h	Remove exception handling support from the old JIT.	2013-05-07 20:53:59 +00:00
TargetRegisterInfo.h	Add TargetRegisterInfo::getCoveringLanes().	2013-05-16 18:03:08 +00:00
TargetSchedule.td	MachineModel: Add a ProcResGroup class.	2013-03-14 21:21:50 +00:00
TargetSelectionDAG.td	Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.	2013-05-22 06:36:09 +00:00
TargetSelectionDAGInfo.h	Track IR ordering of SelectionDAG nodes 2/4.	2013-05-25 02:42:55 +00:00
TargetSubtargetInfo.h	Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.	2013-02-15 22:31:27 +00:00